RMII uses a single centralized system-synchronous 50 MHz clock source (REF_CLK) for both transmit and receive paths across all ports. This simplifies system clocking and lowers pin counts in high port density systems, because your design can use a single board oscillator as opposed to per port TX_CLK/RX_CLK source synchronous clock pairs.
RMII uses two-bit wide transmit and receive data paths. All data and control signals are synchronous to the REF_CLK rising edge. The RX_ER control signal is not used. In 10Mbps mode, all data and control signals are held valid for 10 REF_CLK clock cycles.
Interface Clocking Scheme
EMACs and RMII PHYs can provide the 50 MHz REF_CLK source. Using clock resources already present such as HPS_OSC_CLK input, internal PLLs further simplifies system clocking design and eliminates the need for an additional clock source.
This section discusses system design scenarios for both HPS EMAC-sourced and PHY-sourced REF_CLK.
GUIDELINE: Consult the PHY datasheet for specifics on the choice of REF_CLK source in your application.
- HPS-Sourced REF_CLK
- PHY-Sourced REF_CLK
Did you find the information on this page useful?