AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

Download
ID 683117
Date 12/14/2020
Public
Document Table of Contents

2.5.2. HPS SDRAM I/O Locations

The Intel® Agilex™ EMIF for HPS IP includes default pin location assignments for all the external memory interface signals in constraint files created at IP generation time and read by Intel® Quartus® Prime Pro Edition software during design compilation.

GUIDELINE: Intel® recommends that you use these automated default pin location assignments as a starting point.

You may need to modify the default pinout to meet the restrictions shown in this section.

GUIDELINE: Verify the HPS memory controller I/O locations in the Intel® Quartus® Prime project pinout file in the “output_files” sub-folder before finalizing board layout.

By default, Intel® Quartus® Prime generates output reports, log files and programming files in the “output_files” subfolder of the project folder. See the .pin text file after compilation for the pinout for your design, including the pin locations for the HPS EMIF.

GUIDELINE: Make sure all I/O associated with the HPS memory interface are located within the active HPS EMIF I/O banks.

It is critical that you ensure all I/O necessary for a functioning HPS memory interface are located within the active banks for your HPS memory width as shown in the table below:
Table 9.  HPS SDRAM I/O Locations
EMIF Width Bank 2N Lanes Bank 2M Lanes Bank 2L Lanes
3 2 1 0 3 2 1 0 3 2 1 0
16-bit GPIO 16-bit Data NC4 Address/Command/RZQ/RefClk GPIO
16-bit + ECC GPIO 16-bit Data + ECC Address/Command/RZQ/RefClk GPIO
32-bit 32-bit Data NC Address/Command/RZQ/RefClk GPIO
32-bit + ECC 32-bit Data + ECC Address/Command/RZQ/RefClk GPIO
64-bit 64-bit Data NC Address/Command/RZQ/RefClk 64-bit Data
64-bit + ECC 64-bit Data + ECC Address/Command/RZQ/RefClk 64-bit Data + ECC

Pin Assignments

Within a single data lane (which implements a single x8 DQS group):
  • DQ pins must use pins at indices: 1, 2, 3, 6, 7, 8, 9, 10. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
  • DM/DBI pin must use pin at index 11. There is no flexibility.
  • DQS must use pin at index 4, and DQS# must use pin at index 5. There is no flexibility.
  • Place ALERT# pin in I/O bank 2N, Lane 0, pin index 0 or I/O bank 2N, Lane 1, pin index 0. Otherwise, pin index 0 must have "no connect"; unless it is used for HPS REFCLK_P, Address/Command/RZQ/RefClk, or general-purpose I/O, where allowed.
  • Assignment of data lanes must be as illustrated in the above table. You can swap the locations of entire byte lanes (that is, you may swap locations of byte 0 and byte 1) so long as the resulting pin-out uses only the lanes permitted by your HPS EMIF configuration, as shown in the above table.
  • I/O bank 2M Lane 0, 1, and 2 must only be used for Address/Command/RZQ/RefClk, otherwise “no connect”.
  • You must not change placement of the address and command pins from the default.
  • If not using ECC, IO bank 2M Lane 3 must be “no connect”. If using ECC, the ECC DQS group can be in any single data lane that is not otherwise restricted, that is, there is no requirement for the ECC DQS group to be placed in 2M.
  • HPS REFCLK_P must use IO bank 2M Lane 2 pin index 0. HPS REFCLK_N must use IO bank 2M Lane 2 pin index 1.
  • RZQ must use IO bank 2M Lane 2 pin index 2.

DQ/DQS Group Placement

Configuration DQS Group Placement
16 bit Must be placed in I/O lanes 0 and 1 of 2N.
16 bit + ECC Must be placed in I/O lanes 0 and 1 of 2N and I/O lane 3 of 2M.
32 bit Must be placed in 2N.
32 bit + ECC Must be placed in 2N and I/O lane 3 of 2M.
64 bit Must be placed in 2N and 2L.
64 bit + ECC Must be placed in 2N, 2L, and I/O lane 3 of 2M.
Note: In all cases, the DQ/DQS groups can be swapped around in the I/O banks shown. There is no requirement for the ECC DQS group to be placed in 2M.

Unused HPS EMIF I/O Availability as FPGA GPIO

  • Bank 2N (Data[31:0])—Unused lanes for 16-bit interfaces are available for FPGA GPIO.
  • Band 2M (Addr/Cmd/ECC)
    • Lanes 0, 1, 2 are NOT AVAILABLE as FPGA GPIO
    • Lane 3 is NOT AVAILABLE as FPGA GPIO when not using ECC
  • Bank 2L (Data[63:32])—Unused lanes for 32-bit or less interfaces are available as FPGA GPIO
4 NC indicates "no connect".

Did you find the information on this page useful?

Characters remaining:

Feedback Message