AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
Public
Document Table of Contents

2.6. HPS Memory Debug

GUIDELINE: Verify the memory interface is operational using an FPGA EMIF and the external memory tool kit.

Because the HPS SDRAM controller does not support the external memory interface toolkit, verify that the memory interface is operational using the non-HPS memory controller first. Create a design that instantiates the FPGA memory controller and routes it to the same I/O that the HPS memory controller uses. Once you have verified that the interface is operational with the EMIF toolkit, ensure that you properly instantiate the Intel® Stratix® 10 External Memory Interfaces for HPS IP as described in the sub-section on Instantiating the Intel® Stratix® 10 EMIF IP described in the "Compiling Intel® Stratix® 10 EMIF IP with the Intel® Quartus® Prime Software" section of the External Memory Interface Handbook Volume 3: Reference Material.

For more information, refer to the following documentation:
  • External Memory Interface Handbook Volume 3: Reference Material
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide
  • Intel® Stratix® 10 Device Pin-Out Files

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