External Memory Interfaces Intel Stratix 10 FPGA IP User Guide
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.4 |
IP Version 19.2.2 |
1. Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 19.2.2 |
Intel® Quartus® Prime | 20.4 |
Release Date | 2020.12.14 |
2. External Memory Interfaces Intel Stratix 10 FPGA IP Introduction
You can easily implement the EMIF IP core functions through the Intel® Quartus® Prime software. The Intel® Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA.
The External Memory Interfaces Intel® Stratix® 10 FPGA IP (referred to hereafter as the Intel® Stratix® 10 EMIF IP) provides the following components:
- A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
- A memory controller which implements all the memory commands and protocol-level requirements.
For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator.
Intel® Stratix® 10 EMIF IP Protocol and Feature Support
- Supports DDR4, DDR3, and DDR3L protocols with hard memory controller and hard PHY.
- Supports QDR-IV, QDR II + Xtreme, QDR II +, and QDR II using soft memory controller and hard PHY.
- Supports RLDRAM 3 using third-party soft controller.
- Supports UDIMM, RDIMM, LRDIMM and SODIMM memory devices.
- Supports 3D Stacked Die for DDR4 devices.
- Supports up to 4 physical ranks.
- Supports Ping Pong PHY mode, allowing two memory controllers to share command, address, and control pins.
- Supports error correction code (ECC) for both hard memory controller and soft memory controller.
2.1. Intel Stratix 10 EMIF IP Design Flow
The following figure shows the design flow to provide the fastest out-of-the-box experience with the EMIF IP.
2.2. Intel Stratix 10 EMIF IP Design Checklist
Design Step | Description | Resources |
---|---|---|
Select an FPGA | Not all Intel FPGAs support all memory types and configurations. To help with the FPGA selection process, refer to these resources. | |
Parameterize the IP | Correct IP parameterization is important for good EMIF IP operation. These resources define the memory parameters during IP generation. | |
Generate initial IP and example design | After you have parameterized the EMIF IP, you can generate the IP, along with an optional example design. Refer to the Quick-Start Guide for a walkthrough of this process. | |
Perform functional simulation | Simulation of the EMIF design helps to determine correct operation. These resources explain how to perform simulation and what differences exist between simulation and hardware implementation. | |
Make pin assignments | For guidance on pin placement, refer to these resources. | |
Perform board simulation | Board simulation helps determine optimal settings for signal integrity, drive strength, as well as sufficient timing margins and eye openings. For guidance on board simulation, refer to these resources. | |
Update board parameters in the IP | Board simulation is important to determine optimal settings for signal integrity, drive strength, and sufficient timing margins and eye openings. For guidance on board simulation refer to the mentioned resources. | |
Verify timing closure | For information regarding compilation, system-level timing closure and timing reports refer to the Timing Closure section of this User Guide. | |
Run the design on hardware | For instructions on how to program a FPGA refer to the Quick-Start Guide section of this User Guide. | |
Debug issues with preceding steps | Operational problems can generally be attributed to one of the following: interface configuration, pin/resource planning, signal integrity, or timing. These resources contain information on typical debug procedures and available tools to help diagnose hardware issues. |
3. Intel Stratix 10 EMIF IP Product Architecture
3.1. Intel Stratix 10 EMIF Architecture: Introduction
The following are key hardware features of the Intel® Stratix® 10 EMIF architecture:
Hard Sequencer
The sequencer employs a hard Nios II processor, and can perform memory calibration for a wide range of protocols. You can share the sequencer among multiple memory interfaces of the same or different protocols.
Hard PHY
The PHY circuitry in Intel® Stratix® 10 devices is hardened in the silicon, which simplifies the challenges of achieving timing closure and minimizing power consumption.
Hard Memory Controller
The hard memory controller reduces latency and minimizes core logic consumption in the external memory interface. The hard memory controller supports the DDR3 and DDR4 memory protocols.
PHY-Only Mode
Protocols that use a hard controller (DDR3, DDR4, and RLDRAM 3), provide a PHY-only option, which generates only the PHY and sequencer, but not the controller. This PHY-only mode provides a mechanism by which to integrate your own custom soft controller.
High-Speed PHY Clock Tree
Dedicated high speed PHY clock networks clock the I/O buffers in Intel® Stratix® 10 EMIF IP. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing the data valid window.
Automatic Clock Phase Alignment
Automatic clock phase alignment circuitry dynamically adjusts the clock phase of core clock networks to match the clock phase of the PHY clock networks. The clock phase alignment circuitry minimizes clock skew that can complicate timing closure in transfers between the FPGA core and the periphery.
Resource Sharing
The Intel® Stratix® 10 architecture simplifies resource sharing between memory interfaces. Resources such as the OCT calibration block, PLL reference clock pin, and core clock can be shared. The hard Nios processor in the I/O subsystem manager (I/O SSM) must be shared across all interfaces in a column.
3.1.1. Intel Stratix 10 EMIF Architecture: I/O Subsystem
The I/O subsystem provides the following features:
- General-purpose I/O registers and I/O buffers
- On-chip termination control (OCT)
- I/O PLLs for external memory interfaces and user logic
- Low-voltage differential signaling (LVDS)
- External memory interface
components, as follows:
- Hard memory controller
- Hard PHY
- Hard Nios processor and calibration logic
- DLL
3.1.2. Intel Stratix 10 EMIF Architecture: I/O Column
- A hardened Nios processor with dedicated memory. This Nios block is referred to as the I/O SSM.
- Up to 13 I/O banks. Each I/O bank contains the hardware necessary for an external memory interface.
3.1.3. Intel Stratix 10 EMIF Architecture: I/O SSM
The I/O SSM includes dedicated memory which stores both the calibration algorithm and calibration run-time data. The hardened Nios II processor and the dedicated memory can be used only by an external memory interface, and cannot be employed for any other use. The I/O SSM can interface with soft logic, such as the debug toolkit, via an Avalon-MM bus.
The I/O SSM is clocked by an on-die oscillator, and therefore does not consume a PLL.
3.1.4. Intel Stratix 10 EMIF Architecture: I/O Bank
Each I/O bank resides in an I/O column, and contains the following components:
- Hard memory controller
- Sequencer components
- PLL and PHY clock trees
- DLL
- Input DQS clock trees
- 48 pins, organized into four I/O lanes of 12 pins each
I/O Bank Usage
The pins in an I/O bank can serve as address and command pins, data pins, or clock and strobe pins for an external memory interface. You can implement a narrow interface, such as a DDR3 or DDR4 x8 interface, with only a single I/O bank. A wider interface of up to 72 bits can be implemented by configuring multiple adjacent banks in a multi-bank interface. Any pins in a bank which are not used by the EMIF IP can serve as general-purpose I/O pins of uncalibrated I/O standard with the same voltage settings.
Every I/O bank includes a hard memory controller which you can configure for DDR3 or DDR4. In a multi-bank interface, only the controller of one bank is active; controllers in the remaining banks are turned off to conserve power.
To use a multi-bank Intel® Stratix® 10 EMIF interface, you must observe the following rules:
- Designate one bank as the address and command bank.
- The address and command bank must contain all the address and command pins.
- The locations of individual address and command pins within the address and command bank must adhere to the pin map defined in the pin table— regardless of whether you use the hard memory controller or not.
- If you do use the hard memory controller, the address and command bank contains the active hard controller.
All the I/O banks in a column are capable of functioning as the address and command bank. However, for minimal latency, you should select the center-most bank of the interface as the address and command bank.
3.1.5. Intel Stratix 10 EMIF Architecture: I/O Lane
Each I/O lane can implement one x8/x9 read capture group (DQS group), with two pins functioning as the read capture clock/strobe pair (DQS/DQS#), and up to 10 pins functioning as data pins (DQ and DM pins). To implement x18 and x36 groups, you can use multiple lanes within the same bank.
It is also possible to implement a pair of x4 groups in a lane. In this case, four pins function as clock/strobe pair, and 8 pins function as data pins. DM is not available for x4 groups. There must be an even number of x4 groups for each interface.
For x4 groups, DQS0 and DQS1 must be placed in the same I/O lane as a pair. Similarly, DQS2 and DQS3 must be paired. In general, DQS(x) and DQS(x+1) must be paired in the same I/O lane.
Group Size | Number of Lanes Used | Maximum Number of Data Pins per Group |
---|---|---|
x8 / x9 | 1 | 10 |
x18 | 2 | 22 |
x36 | 4 | 46 |
pair of x4 | 1 | 4 per group, 8 per lane |
3.1.6. Intel Stratix 10 EMIF Architecture: Input DQS Clock Tree
You can configure an input DQS clock tree in x4 mode, x8/x9 mode, x18 mode, or x36 mode.
Within every bank, only certain physical pins at specific locations can drive the input DQS clock trees. The pin locations that can drive the input DQS clock trees vary, depending on the size of the group.
Group Size | Index of Lanes Spanned by Clock Tree | In-Bank Index of Pins Usable as Read Capture Clock / Strobe Pair | |
---|---|---|---|
Positive Leg | Negative Leg | ||
x4 | 0A | 4 | 5 |
x4 | 0B | 8 | 9 |
x4 | 1A | 16 | 17 |
x4 | 1B | 20 | 21 |
x4 | 2A | 28 | 29 |
x4 | 2B | 32 | 33 |
x4 | 3A | 40 | 41 |
x4 | 3B | 44 | 45 |
x8 / x9 | 0 | 4 | 5 |
x8 / x9 | 1 | 16 | 17 |
x8 / x9 | 2 | 28 | 29 |
x8 / x9 | 3 | 40 | 41 |
x18 | 0, 1 | 8 | 9 |
x18 | 2, 3 | 32 | 33 |
x36 | 0, 1, 2, 3 | 20 | 21 |
3.1.7. Intel Stratix 10 EMIF Architecture: PHY Clock Tree
The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.
The PHY clock tree in Intel® Stratix® 10 devices can run as fast as 1.3 GHz. All Intel® Stratix® 10 external memory interfaces use the PHY clock trees.
3.1.8. Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks
Intel® Stratix® 10 external memory interfaces that span multiple banks use the PLL in each bank. The Intel® Stratix® 10 architecture allows for relatively short PHY clock networks, reducing jitter and duty-cycle distortion.
The following mechanisms ensure that the clock outputs of individual PLLs in a multi-bank interface remain in phase:
- A single PLL reference clock source feeds all PLLs. The reference clock signal reaches the PLLs by a balanced PLL reference clock tree. The Intel® Quartus® Prime software automatically configures the PLL reference clock tree so that it spans the correct number of banks.
- The EMIF IP sets the PLL M and N values appropriately to maintain synchronization among the clock dividers across the PLLs. This requirement restricts the legal PLL reference clock frequencies for a given memory interface frequency and clock rate. The Stratix 10 EMIF IP parameter editor automatically calculates and displays the set of legal PLL reference clock frequencies. If you plan to use an on-board oscillator, you must ensure that its frequency matches the PLL reference clock frequency that you select from the displayed list. The correct M and N values of the PLLs are set automatically based on the PLL reference clock frequency that you select.
3.1.9. Intel Stratix 10 EMIF Architecture: Clock Phase Alignment
The clock phase alignment feature effectively eliminates the clock skew effect in all transfers between the core and the periphery, facilitating timing closure. All Stratix 10 external memory interfaces employ clock phase alignment circuitry.

3.2. Intel Stratix 10 EMIF Sequencer
The Intel® Stratix® 10 EMIF sequencer is responsible for the following operations:
- Initializes memory devices.
- Calibrates the external memory interface.
- Governs the hand-off of control to the memory controller.
- Handles recalibration requests and debug requests.
- Handles all supported protocols and configurations.
3.2.1. Intel Stratix 10 EMIF DQS Tracking
DQS tracking is enabled for QDRII/II+/II+ Xtreme, QDR-IV, and RLDRAM 3 protocols; it is not available for DDR3 and DDR4 protocols. For QDRII/II+/II+ Xtreme, QDR-IV, and RLDRAM 3, DQS tracking does not need a specific command to initiate tracking, because the read capture clock/strobe is free running. Tracking happens constantly and automatically when the circuitry is enabled.
3.3. Intel Stratix 10 EMIF Calibration
The calibration process enables the system to compensate for the effects of factors such as the following:
- Timing and electrical constraints, such as setup/hold time and Vref variations.
- Circuit board and package factors, such as skew, fly-by effects, and manufacturing variations.
- Environmental uncertainties, such as variations in voltage and temperature.
- The demanding effects of small margins associated with high-speed operation.
For a given external memory interface, calibration occurs in parallel for all DQS groups and I/O banks. For an I/O column containing multiple external memory interfaces, there is no particular calibration order in relation to the interfaces; however, for a given SRAM Object File (.sof), calibration will always occur in the same order.
3.3.1. Intel Stratix 10 Calibration Stages
The stages of calibration vary, depending on the protocol of the external memory interface.
Stage | DDR4 | DDR3 | RLDRAM 3 | QDR-IV | QDR II/II+ |
---|---|---|---|---|---|
Address and command | |||||
Leveling | Yes | Yes | — | — | — |
Deskew | Yes | — | — | Yes | — |
Read | |||||
DQSen | Yes | Yes | Yes | Yes | Yes |
Deskew | Yes | Yes | Yes | Yes | Yes |
VREF-In | Yes | — | — | Yes | — |
LFIFO | Yes | Yes | Yes | Yes | Yes |
Write | |||||
Leveling | Yes | Yes | Yes | Yes | — |
Deskew | Yes | Yes | Yes | Yes | Yes |
VREF-Out | Yes | — | — | — | — |
3.3.2. Intel Stratix 10 Calibration Stages Descriptions
Address and Command Calibration
The goal of address and command calibration is to delay address and command signals as necessary to optimize the address and command window. This stage is not available for all protocols, and cannot compensate for a poorly implemented board design.
- Leveling calibration— Centers the CS# signal and the entire address and command bus, relative to the CK clock. This operation is available for DDR3 and DDR4 interfaces only.
- Deskew calibration— Provides per-bit deskew for the address and command bus (except CS#), relative to the CK clock. This operation is available for DDR4 and QDR-IV interfaces only.
Read Calibration
Read calibration consists of the following parts:
- DQSen calibration— Calibrates the timing of the read capture clock gating and ungating, so that the PHY can gate and ungate the read clock at precisely the correct time—if too early or too late, data corruption can occur. The algorithm for this stage varies, depending on the memory protocol.
- Deskew calibration— Performs per-bit deskew of read data relative to the read strobe or clock.
- VREF-In calibration— Calibrates the VREF level at the FPGA.
- LFIFO calibration: Normalizes differences in read delays between groups due to fly-by, skews, and other variables and uncertainties.
Write Calibration
Write calibration consists of the following parts:
- Leveling calibration— Aligns the write strobe and clock to the memory clock, to compensate for skews, especially those associated with fly-by topology. The algorithm for this stage varies, depending on the memory protocol.
- Deskew calibration— Performs per-bit deskew of write data relative to the write strobe and clock.
- VREF-Out calibration— Calibrates the VREF level at the memory device.
3.3.3. Intel Stratix 10 Calibration Flowchart
3.3.4. Intel Stratix 10 Calibration Algorithms
Address and Command Calibration
Address and command calibration consists of the following parts:
- Leveling calibration— (DDR3 and DDR4 only) Toggles the CS# and CAS# signals to send read commands while keeping other address and command signals constant. The algorithm monitors for incoming DQS signals, and if the DQS signal toggles, it indicates that the read commands have been accepted. The algorithm then repeats using different delay values, to find the optimal window.
- Deskew calibration— (DDR4 and
QDR-IV
only)
- (DDR4) Uses the
DDR4 address and command parity feature. The FPGA sends the address and
command parity bit, and the DDR4 memory device responds with an alert
signal if the parity bit is detected. The alert signal from the memory
device tells the FPGA that the parity bit was received.
Deskew calibration requires use of the PAR/ALERT# pins, so you should not omit these pins from your design. One limitation of deskew calibration is that it cannot deskew ODT and CKE pins.
- (QDR-IV) Uses
the QDR-IV loopback mode. The FPGA sends address and command signals,
and the memory device sends back the address and command signals which
it captures, via the read data pins. The returned signals indicate to
the FPGA what the memory device has captured. Deskew calibration can
deskew all synchronous address and command signals. Note: For more information about loopback mode, refer to your QDR-IV memory device data sheet.
- (DDR4) Uses the
DDR4 address and command parity feature. The FPGA sends the address and
command parity bit, and the DDR4 memory device responds with an alert
signal if the parity bit is detected. The alert signal from the memory
device tells the FPGA that the parity bit was received.
Read Calibration
- DQSen calibration— (DDR3, DDR4,
RLDRAMx and QDRx)
DQSen calibration occurs before Read deskew, therefore only a single DQ bit is
required to pass in order to achieve a successful read pass.
- (DDR3 and DDR4) The DQSen calibration algorithm searches the DQS preamble using a hardware state machine. The algorithm sends many back-to-back reads with a one clock cycle gap between. The hardware state machine searches for the DQS gap while sweeping DQSen delay values. The algorithm then increments the VFIFO value, and repeats the process until a pattern is found. The process is then repeated for all other read DQS groups.
- (RLDRAMx and QDRx) The DQSen calibration algorithm does not use a
hardware state machine; rather, it calibrates cycle-level delays using
software and subcycle delays using DQS tracking hardware. The algorithm
requires good data in memory, and therefore relies on guaranteed writes.
(Writing a burst of 0s to one location, and a burst of 1s to another;
back-to-back reads from these two locations are used for read
calibration.)
The algorithm enables DQS tracking to calibrate the phase component of DQS enable, and then issues a guaranteed write, followed by back-to-back reads. The algorithm sweeps DQSen values cycle by cycle until the read operation succeeds. The process is then repeated for all other read groups.
- Deskew calibration—
Read deskew calibration is performed before write leveling, and must be
performed at least twice: once before write calibration, using simple data
patterns from guaranteed writes, and again after write calibration, using
complex data patterns.
The deskew calibration algorithm performs a guaranteed write, and then sweeps dqs_in delay values from low to high, to find the right edge of the read window. The algorithm then sweeps dq-in delay values low to high, to find the left edge of the read window. Updated dqs_in and dq_in delay values are then applied to center the read window. The algorithm then repeats the process for all data pins.
- Vref-In calibration— Read Vref-In calibration begins by programming Vref-In with an arbitrary value. The algorithm then sweeps the Vref-In value from the starting value to both ends, and measures the read window for each value. The algorithm selects the Vref-In value which provides the maximum read window.
- LFIFO calibration— Read LFIFO calibration normalizes read delays between groups. The PHY must present all data to the controller as a single data bus. The LFIFO latency should be large enough for the slowest read data group, and large enough to allow proper synchronization across FIFOs.
Write Calibration
- Leveling calibration—
Write leveling calibration aligns the write strobe and clock to the memory
clock, to compensate for skews. In general, leveling calibration tries a variety
of delay values to determine the edges of the write window, and then selects an
appropriate value to center the window. The details of the algorithm vary,
depending on the memory protocol.
- (DDRx) Write leveling occurs before write deskew, therefore only one successful DQ bit is required to register a pass. Write leveling staggers the DQ bus to ensure that at least one DQ bit falls within the valid write window.
- (RLDRAMx) Optimizes for the CK versus DK relationship.
- (QDR-IV) Optimizes for the CK versus DK relationship. Is covered by address and command deskew using the loopback mode.
- (QDR II/II+/Xtreme) The K clock is the only clock, therefore write leveling is not required.
- Deskew calibration— Performs per-bit deskew of write data relative to the write strobe and clock. Write deskew calibration does not change dqs_out delays; the write clock is aligned to the CK clock during write leveling.
- VREF-Out calibration— (DDR4) Calibrates the VREF level at the memory device. The VREF-Out calibration algorithm is similar to the VREF-In calibration algorithm.
3.4. Intel Stratix 10 EMIF IP Controller
3.4.1. Hard Memory Controller
The hard memory controller implements efficient pipelining techniques and advanced dynamic command and data reordering algorithms to improve bandwidth usage and reduce latency, providing a high performance solution.
The controller architecture is modular and fits in a single I/O bank. The structure allows you to:
- Configure each I/O bank
as either:
- A control path that drives all the address and command pins for the memory interface.
- A data path that drives up to 32 data pins for DDR-type interfaces.
- Place your memory controller in any location.
- Pack up multiple banks together to form memory interfaces of different widths up to 72 bits.
- Bypass the hard memory controller and use your own custom IP if required.

The hard memory controller consists of the following logic blocks:
- Core and PHY interfaces
- Main control path
- Data buffer controller
- Read and write data buffers
The core interface supports the Avalon® Memory-Mapped (Avalon-MM) interface. The interface communicates to the PHY using the Altera PHY Interface (AFI). The whole control path is split into the main control path and the data buffer controller.
3.4.1.1. Hard Memory Controller Features
Feature | Description |
---|---|
Memory standards support |
Supports the following memory standards:
|
Memory devices support | Supports the following memory devices:
|
3D Stacked Die support | Supports 2 and 4 height of 3D stacked die for DDR4 to increase memory capacity. |
Memory controller bypass mode | You can use this configurable mode to bypass the hard memory controller and use your own customized controller. |
Ping-Pong controller mode | You can use this configurable mode to enable two memory controllers to time-share the same set of address and command pins. |
Interface protocols support |
|
Rate support | The hard memory controller runs at half rate. It can accept memory access commands from the core logic at half rate or quarter rate. |
Configurable memory interface width | Supports data widths from 8 to 72 bits, in 8 bit increments |
Multiple ranks support | Supports:
|
Burst adapter |
Able to accept burst lengths of 1–127 on the local interface of the controller and map the bursts to efficient memory commands. For applications that must strictly adhere to the Avalon® -MM specification, the maximum burst length is 64. No burst chop support for DDR3 and DDR4. |
Efficiency optimization features |
|
User requested priority | You can assign priority to commands. This feature allows you to specify that higher priority commands are issued earlier to reduce latency. |
Starvation counter | Ensures all requests are served after a predefined time out period, which ensures that low priority access are not left behind while reordering data for efficiency. |
Timing for address/command bus |
To maximize command bandwidth, you can double the number of memory commands in one controller clock cycle:
Note: Quasi-1T and Quasi-2T addressing is not
supported for Ping Pong PHY.
|
Bank interleaving | Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses. |
On-die termination | The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design. |
Refresh features |
|
ECC support |
|
DQS tracking | Tracks the DQS timing and makes auto adjustments to align to the DQS edges. |
Power saving features |
|
Mode register set | Access the memory mode register. |
DDR4 features |
|
User ZQ calibration | Long or short ZQ calibration request for DDR3 or DDR4. |
3.4.1.2. Hard Memory Controller Main Control Path
- Contains the command processing pipeline.
- Monitors all the timing parameters.
- Keeps track of dependencies between memory access commands.
- Guards against memory access hazards.
Component | Description |
---|---|
Input interface |
|
Command generator and burst adapter |
|
Timing Bank Pool |
|
Arbiter |
|
Global Timer |
Tracks the global timing constraints including:
|
MMR/IOCSR |
|
Sideband |
Executes the refresh and power down features. |
ECC controller |
Although ECC encoding and decoding is performed in soft logic1, the ECC controller maintains the read-modify-write state machine in the hard solution. |
AFI interface |
The memory controller communicates with the PHY using this interface. |
3.4.1.3. Data Buffer Controller
- Manages the read and
write access to the data buffers:
- Provides the data storing pointers to the buffers when the write data is accepted or the read return data arrives.
- Provides the draining pointer when the write data is dispatched to memory or the read data is read out of the buffer and sent back to users.
- Satisfies the required write latency.
- If ECC support is enabled, assists the main control path to perform read-modify-write.
Data reordering is performed with the data buffer controller and the data buffers.
Each I/O bank contains two data buffer controller blocks for the data buffer lanes that are split within each bank. To improve your timing, place the data buffer controller physically close to the I/O lanes.
3.4.2. Intel Stratix 10 Hard Memory Controller Rate Conversion Feature
To facilitate timing closure, you may choose to clock your core user logic at quarter-rate, resulting in easier timing closure at the expense of increased area and latency. To improve efficiency and help reduce overall latency, you can run the hard memory controller and PHY at half rate.
The rate conversion feature converts traffic from the FPGA core to the hard memory controller from quarter-rate to half-rate, and traffic from the hard memory controller to the FPGA core from half-rate to quarter-rate. From the perspective of user logic inside the FPGA core, the effect is the same as if the hard memory controller were running at quarter-rate.
The rate conversion feature is enabled automatically during IP generation whenever all of the following conditions are met:
- The hard memory controller is in use.
- User logic runs at quarter-rate.
- The interface targets either an ES2 or production device.
- Running the hard memory controller at half-rate does not exceed the fMax specification of the hard memory controller and hard PHY.
When the rate conversion feature is enabled, you should see the following info message displayed in the IP generation GUI:
PHY and controller running at 2x the frequency of user logic for improved efficiency.3.5. Hardware Resource Sharing Among Multiple Intel Stratix 10 EMIFs
3.5.1. I/O SSM Sharing
When a column contains multiple memory interfaces, the Nios® II processor calibrates each interface serially. Interfaces placed within the same I/O column always share the same I/O SSM. The Intel® Quartus® Prime Fitter handles I/O SSM sharing automatically.
3.5.2. I/O Bank Sharing
Rules for Sharing I/O Banks
- A bank cannot serve as the address
and command bank for more than one interface. This means that lanes which
implement address and command pins for different interfaces cannot be allocated
to the same physical bank. Note: An exception to the above rule exists when two interfaces are configured in a Ping-Pong PHY fashion. In such a configuration, two interfaces share the same set of address and command pins, effectively meaning that they share the same address and command tile.
- Pins within a lane cannot be shared by multiple memory interfaces.
- Any pins in a bank which are not used by the EMIF IP can serve as general-purpose I/O pins of uncalibrated I/O standard with the same voltage settings.
- You can configure a bank as LVDS or as EMIF, but not both at the same time.
- Interfaces that share banks must reside at adjacent bank locations.
The following diagram illustrates two x16 interfaces sharing an I/O bank. The two interfaces share the same clock phase alignment block, so that one core clock signal can interact with both interfaces. Without sharing, the two interfaces would occupy a total of four physical banks instead of three.
3.5.3. PLL Reference Clock Sharing
To share a PLL reference clock, the following requirements must be met:
- Interfaces must expect a reference clock signal of the same frequency.
- Interfaces must be placed in the same column.
- Interfaces must be placed at adjacent bank locations.
3.5.4. Core Clock Network Sharing
You might want to share core clock networks for the following reasons:
- To minimize the area and latency penalty associated with clock domain crossing.
- To minimize consumption of core clock networks.
Multiple memory interfaces can share the same core clock signals under the following conditions:
- The memory interfaces have the same protocol, rate, frequency, and PLL reference clock source.
- The interfaces reside in the same I/O column.
- The interfaces reside in adjacent bank locations.
For multiple memory interfaces to share core clocks, you must specify one of the interfaces as master and the remaining interfaces as slaves. Use the Core clocks sharing setting in the parameter editor to specify the master and slaves.
In your RTL, connect the clks_sharing_master_out signal from the master interface to the clks_sharing_slave_in signal of all the slave interfaces. Both the master and slave interfaces expose their own output clock ports in the RTL (e.g. emif_usr_clk, afi_clk), but the signals are equivalent, so it does not matter whether a clock port from a master or a slave is used.
Core clock sharing necessitates PLL reference clock sharing; therefore, only the master interface exposes an input port for the PLL reference clock. All slave interfaces use the same PLL reference clock signal.
3.6. User-requested Reset in Intel Stratix 10 EMIF IP
Description | |
---|---|
Reset-related signals |
local_reset_req (input) local_reset_done (output) |
When can user logic request a reset? |
local_reset_req has effect only when local_reset_done is high. After device power-on, the local_reset_done signal transitions high after the completion of the first calibration, whether the calibration is successful or not. In subsequent calibration in user mode, the local_reset_done signal transitions high once the calibration is completed. The local_reset_done signal takes more time to transition high in first calibration after device power-on as more operations are required put the PHY into working state. |
Is user-requested reset a requirement? |
A user-requested reset is optional. The I/O SSM automatically ensures that the memory interface begins from a known state as part of the device power-on sequence. A user-requested reset is necessarily only if the user logic must explicitly reset a memory interface after the device power-on sequence. |
When does a user-requested reset actually happen? |
A reset request is handled by the I/O SSM. If the I/O SSM receives a reset request from multiple interfaces within the same I/O column, it must serialize the reset sequence of the individual interfaces. You should avoid making assumptions on when the reset sequence will begin after a request is issued. |
Timing requirement and triggering mechanism. |
Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
How long can an external memory interface be kept in reset? |
It is not possible to keep an external memory interface in reset indefinitely. Asserting local_reset_req high continuously has no effect as a reset request is completed by a full 0->1->0 pulse. |
Delaying initial calibration. |
Initial calibration cannot be skipped. The local_reset_done signal is driven high only after initial calibration has completed. |
Reset scope (within an external memory interface). |
Only circuits that are required to restore EMIF to power-up state are reset. Excluded from the reset sequence are the IOSSM, the IOPLL(s), the DLL(s), and the CPA. |
Reset scope (within an I/O column). |
local_reset_req is a per-interface reset. |
Method for Initiating a User-requested Reset
Step 1 - Precondition
Before asserting local_reset_req, user logic must ensure that the local_reset_done signal is high.
As part of the device power-on sequence, the local_reset_done signal automatically transitions to high upon the completion of the interface calibration sequence, regardless of whether calibration is successful or not.
Step 2 - Reset Request
After the pre-condition is satisfied, user logic can send a reset request by driving the local_cal_req signal from low to high and then low again (that is, by sending a pulse of 1).
- The low-to-high and high-to-low transitions can occur asychronously; that is, they need not happen in relation to any clock edges. However, the pulse must meet a minimum pulse width of at least 2 EMIF core clock cycles. For example, if the emif_usr_clk has a period of 4ns, then the local_reset_req pulse must last at least 8ns (that is, two emif_usr_clk periods).
- The reset request is considered complete only after the high-to-low transition. The EMIF IP does not initiate the reset sequence when the local_reset_req is simply held high.
- Additional pulses to local_reset_req are ignored until the reset sequence is completed.
Optional - Detecting local_reset_done deassertion and assertion
If you want, you can monitor the status of the local_reset_done signal to explicitly detect the status of the reset sequence.
- After the EMIF IP receives a reset request, it deasserts the local_reset_done signal. After initial power-up calibration, local_reset_done is de-asserted only in response to a user-requested reset. The reset sequence is imminent when local_reset_done has transitioned to low, although the exact timing depends on the current state of the I/O SSM. As part of the EMIF reset sequence, the core reset signal (emif_usr_reset_n, afi_reset_n) is driven low. Do not use a register reset by the core reset signal to sample local_reset_done.
- After the reset sequence has completed, local_reset_done is driven high again. local_reset_done being driven high indicates the completion of the reset sequence and the readiness to accept a new reset request; however, it does not imply that calibration was successful or that the hard memory controller is ready to accept requests. For these purposes, user logic must check signals such as afi_cal_success, afi_cal_fail, and amm_ready.
3.7. Intel Stratix 10 EMIF for Hard Processor Subsystem
To enable connectivity between the Intel® Stratix® 10 HPS and the Intel® Stratix® 10 EMIF IP, you must create and configure an instance of the Intel® Stratix® 10 External Memory Interface for HPS IP core, and use Platform Designer to connect it to the Intel® Stratix® 10 Hard Processor Subsystem instance in your system.
Supported Modes
The Intel® Stratix® 10 Hard Processor Subsystem is compatible with the following external memory configurations:
Protocol | DDR3, DDR4 |
Maximum memory clock frequency |
DDR3: 933 MHz DDR4: 1200 MHz
|
Configuration | Hard PHY with hard memory controller |
Clock rate of PHY and hard memory controller | Half-rate |
Data width (without ECC) | 16-bit, 32-bit, 64-bit |
Data width (with ECC) | 24-bit, 40-bit, 72-bit |
DQ width per group | x8 |
Maximum number of I/O lanes for address/command | 3 |
Memory format | Discrete, UDIMM, SODIMM, RDIMM |
Ranks / CS# width | Up to 2 |
3.7.1. Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with HPS
The restrictions on I/O bank usage result from the Intel® Stratix® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed.
The following diagram illustrates the use of I/O banks and lanes for various EMIF-HPS data widths:
The HPS EMIF uses the closest located external memory interfaces I/O banks to connect to SDRAM.
The following diagram illustrates restrictions on I/O pin usage. Refer to the text following the diagram for a detailed explanation of these restrictions.


If no HPS EMIF is used in a system, the entire HPS EMIF bank can be used as FPGA general purpose I/O. If there is an HPS EMIF in a system, the unused HPS EMIF pins can be used as FPGA general purpose I/O, with the following restrictions:
- Bank 2M:
- Lane 3 of Bank 2M is used for data bits only when ECC mode is active. Whether ECC is active or not, you must not put general purpose I/Os in this lane.
- Lanes 2, 1, and 0 are used for SDRAM address and command. Unused pins in these lanes should not be used by the FPGA fabric, because their operation cannot be guaranteed.
- Bank 2N and Bank 2L :
- Lanes 3, 2, 1, and 0 are used for data bits.
- With 64-bit data widths, unused pins in these banks should not be used by the FPGA fabric, because their operation cannot be guaranteed.
- With 32-bit data widths, unused pins in Bank 2N should not be used by the FPGA fabric, because their operation cannot be guaranteed. Lanes 0-3 of bank 2L are not used by the HPS EMIF, therefore any pins within these lanes can be used by the FPGA fabric.
- With 16-bit data widths, Intel® Quartus® Prime assigns lane 0 and lane 1 as data lanes in bank 2N. Unused pins in these two lanes should not be used by the FPGA fabric, because their operation cannot be guaranteed. Lanes 2 and 3 are not used by the HPS EMIF, therefore pins within these lanes can be used by the FPGA fabric.
By default, the Intel® Stratix® 10 External Memory Interface for HPS IP core together with the Intel® Quartus® Prime Fitter automatically implements a starting point placement which you may need to modify. You must adhere to the following requirements, which are specific to HPS EMIF:
- Within a single data lane (which implements a single x8 DQS
group):
- DQ pins must use pins at indices 1, 2, 3, 6, 7, 8, 9, 10. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
- DM/DBI pin must use pin at index 11. There is no flexibility.
- DQS and DQS# must use pins at index 4 and 5, respectively. There is no flexibility.
- Pin index 0 must have no connection, unless used for alert# or HPS REFCLK_P, or address/command, or general-purpose I/O, where allowed.
- The above figures show an overview of how the data lanes are
used, depending on the width of the interface. The following table shows the I/O
bank and I/O lanes that you must use, depending on the width and configuration
of the interface.
Configuration DQS Group Placement 16 bit Must be placed in I/O lanes 0 and 1 of 2N. 16 bit + ECC Must be placed in I/O lanes 0 and 1 of 2N and I/O lane 3 of 2M. 32 bit Must be placed in 2N. 32 bit + ECC Must be placed in 2N and I/O lane 3 of 2M. 64 bit Must be placed in 2N and 2L. 64 bit + ECC Must be placed in 2N, 2L, and I/O lane 3 of 2M. Note:- In all cases, the DQS groups can be swapped around in the I/O banks shown. There is no requirement for the ECC DQS group to be placed in bank 2M.
- I/O lane 3 of bank 2M cannot be used if ECC is turned off. You must not put general purpose I/Os in lane 3 of bank 2M.
- You must not change placement of the address and command pins from the default placement in I/O bank 2M.
- The alert# pin must be at index 0 (of any lane of any bank) and must be grouped with its Intel® Quartus® Prime software-assigned DQS group, or must be in any unused pin within address and command section. Bank 2N, lane 0, index 0 or bank 2N, lane 1, index 0 are the recommended locations for alert# for new designs. This allows for maximum flexibility of different interface widths. Existing (working) designs with alert#, on unused address and command pins, or in other data I/O lanes at index 0, is allowed.
- The PLL reference clock must be placed in I/O bank 2M with the address and command pins. Failure to do this will cause device configuration problems. The PLL reference clock must be running at the correct frequency before device configuration occurs.
- The RZQ pin must be placed in I/O bank 2M with the address and command pins. Failure to do this will cause Fitter or device configuration problems.
To override the default generated pin assignments, comment out the relevant HPS_LOCATION assignments in the .qip file, and add your own location assignments (using set_location_assignment) in the .qsf file.
3.7.2. Using the Legacy EMIF Debug Toolkit with Intel Stratix 10 HPS Interfaces
To debug your Intel® Stratix® 10 HPS interface using the Legacy EMIF Debug Toolkit, you should create an identically parameterized, non-HPS version of your interface, and apply the toolkit to that interface. When you finish debugging this non-HPS interface, you can then apply any needed changes to your HPS interface, and continue your design development.
3.7.3. HPS EMIF Simulation
3.8. Intel Stratix 10 EMIF Ping Pong PHY
In Intel® Stratix® 10 EMIF, Ping Pong PHY supports both half-rate and quarter-rate interfaces for DDR3, and quarter-rate for DDR4.
3.8.1. Intel Stratix 10 Ping Pong PHY Feature Description
With the Ping Pong PHY, address and command signals from two independent controllers are multiplexed onto shared buses by delaying one of the controller outputs by one full-rate clock cycle. The result is 1T timing, with a new command being issued on each full-rate clock cycle. The following figure shows address and command timing for the Ping Pong PHY.
The command signals CS, ODT, and CKE have two signals (one for ping and one for pong); the other address and command signals are shared.
3.8.2. Intel Stratix 10 Ping Pong PHY Architecture
The hard memory controller I/O bank of the primary interface is used for address and command and is always adjacent and above the hard memory controller bank of the secondary interface. All four lanes of the primary hard memory controller bank are used for address and command.
The following example shows a 2x16 Ping Pong PHY bank-lane configuration. The upper bank (I/O bank N) is the address and command bank, which serves both the primary and secondary interfaces. The primary hard memory controller is linked to the secondary interface by the Ping Pong bus. The lower bank (I/O bank N-1) is the secondary interface bank, which carries the data buses for both primary and secondary interfaces. In the 2x16 case a total of four I/O banks are required for data, hence two banks in total are sufficient for the implementation.
The data for the primary interface is routed down to the top two lanes of the secondary I/O bank, and the data for the secondary interface is routed to the bottom two lanes of the secondary I/O bank.
A 2x32 interface can be implemented similarly, with the additional data lanes placed above and below the primary and secondary I/O banks, such that primary data lanes are placed above the primary bank and secondary data lanes are placed below the secondary bank.
3.8.3. Intel Stratix 10 Ping Pong PHY Limitations
Ping Pong PHY uses all lanes of the address and command I/O bank as address and command. For information on pin allocations, refer to the pin-out file for your device, at Pin-Out Files for Intel FPGA Devices on www.altera.com.
An additional limitation is that I/O lanes may be left unused when you instantiate multiple pairs of Ping Pong PHY interfaces. The following diagram shows two pairs of x8 Pin Pong controllers (a total of 4 interfaces). Lanes highlighted in yellow are not driven by any memory interfaces (unused lanes and pins can still serve as general purpose I/Os). Even with some I/O lanes left unused, the Ping Pong PHY approach is still beneficial in terms of resource usage, compared to independent interfaces. Memory widths of 24 bits and 40 bits have a similar situation, while 16 bit, 32 bit, and 64 bit memory widths do not suffer this limitation.
3.8.4. Intel Stratix 10 Ping Pong PHY Calibration
Calibration of a Ping Pong PHY interface incorporates two sequencers, one on the primary hard memory controller I/O bank, and one on the secondary hard memory controller I/O bank. To ensure that the two sequencers issue instructions on the same memory clock cycle, the Nios II processor configures the sequencer on the primary hard memory controller to receive a token from the secondary interface, ignoring any commands from the Avalon bus. Additional delays are programmed on the secondary interface to allow for the passing of the token from the sequencer on the secondary hard memory controller tile to the sequencer on the primary hard memory controller tile. During calibration, the Nios II processor assumes that commands are always issued from the sequencer on the primary hard memory controller I/O bank. After calibration, the Nios II processor adjusts the delays for use with the primary and secondary hard memory controllers.
3.8.5. Using the Ping Pong PHY
- Configure a single memory interface according to your requirements.
-
Select Instantiate two controllers sharing a Ping Pong
PHY on the General tab in
the parameter editor.
The Intel® Quartus® Prime software replicates the interface, resulting in two memory controllers and a shared PHY. The system configures the I/O bank-lane structure, without further input from you.
3.8.6. Ping Pong PHY Simulation Example Design
Functionally, the IP interfaces with user traffic separately, as it would with two independent memory interfaces. You can also generate synthesizable example designs, where the external memory interface IP interfaces with a traffic generator.
4. Intel Stratix 10 EMIF IP End-User Signals
4.1. Interface and Signal Descriptions
4.1.1. Intel Stratix 10 EMIF IP Interfaces for DDR3
Interface Name | Interface Type | Description |
---|---|---|
local_reset_req | Conduit | Local reset request. Output signal from local_reset_combiner |
local_reset_status | Conduit | Local reset status. Input signal to the local_reset_combiner |
pll_ref_clk | Clock Input | PLL reference clock input |
pll_locked | Conduit | PLL locked signal |
pll_extra_clk_0 | Clock Output | Additional core clock 0 |
pll_extra_clk_1 | Clock Output | Additional core clock 1 |
pll_extra_clk_2 | Clock Output | Additional core clock 2 |
pll_extra_clk_3 | Clock Output | Additional core clock 3 |
oct | Conduit | On-Chip Termination (OCT) interface |
mem | Conduit | Interface between FPGA and external memory |
status | Conduit | PHY calibration status interface |
afi_reset_n | Reset Output | AFI reset interface |
afi_clk | Clock Output | AFI clock interface |
afi_half_clk | Clock Output | AFI half-rate clock interface |
afi | Conduit | Altera PHY Interface (AFI) |
emif_usr_reset_n | Reset Output | User clock domain reset interface |
emif_usr_clk | Clock Output | User clock interface |
emif_usr_reset_n_sec | Reset Output | User clock domain reset interface (for the secondary interface in ping-pong configuration) |
emif_usr_clk_sec | Clock Output | User clock interface (for the secondary interface in ping-pong configuration) |
cal_debug_reset_n | Reset Input | User calibration debug clock domain reset interface |
cal_debug_clk | Clock Input | User calibration debug clock interface |
cal_debug_out_reset_n | Reset Output | User calibration debug clock domain reset interface |
cal_debug_out_clk | Clock Output | User calibration debug clock interface |
clks_sharing_master_out | Conduit | Core clocks sharing master interface |
clks_sharing_slave_in | Conduit | Core clocks sharing slave input interface |
clks_sharing_slave_out | Conduit | Core clocks sharing slave output interface |
ctrl_amm | Avalon Memory-Mapped Slave | Controller Avalon Memory-Mapped interface |
ctrl_auto_precharge | Conduit | Controller auto-precharge interface |
ctrl_user_priority | Conduit | Controller user-requested priority interface |
ctrl_ecc_user_interrupt | Conduit | Controller ECC user interrupt interface |
ctrl_ecc_readdataerror | Conduit | Controller ECC read data error indication interface |
ctrl_ecc_status | Conduit | Controller ECC status interface |
ctrl_mmr_slave | Avalon Memory-Mapped Slave | Controller MMR slave interface |
hps_emif | Conduit | Conduit between Hard Processor Subsystem and memory interface |
cal_debug | Avalon Memory-Mapped Slave | Calibration debug interface |
cal_debug_out | Avalon Memory-Mapped Master | Calibration debug interface |
4.1.1.1. local_reset_req for DDR3
Port Name | Direction | Description |
---|---|---|
local_reset_req | Input | Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
4.1.1.2. local_reset_status for DDR3
Port Name | Direction | Description |
---|---|---|
local_reset_done | Output | Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. |
4.1.1.3. pll_ref_clk for DDR3
Port Name | Direction | Description |
---|---|---|
pll_ref_clk | Input | PLL reference clock input |
4.1.1.4. pll_locked for DDR3
Port Name | Direction | Description |
---|---|---|
pll_locked | Output | PLL lock signal to indicate whether the PLL has locked |
4.1.1.5. pll_extra_clk_0 for DDR3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_0 | Output | PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.1.6. pll_extra_clk_1 for DDR3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_1 | Output | PLL extra core clock signal output 1. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.1.7. pll_extra_clk_2 for DDR3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_2 | Output | PLL extra core clock signal output 2. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.1.8. pll_extra_clk_3 for DDR3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_3 | Output | PLL extra core clock signal output 3. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.1.9. oct for DDR3
Port Name | Direction | Description |
---|---|---|
oct_rzqin | Input | Calibrated On-Chip Termination (OCT) RZQ input pin |
4.1.1.10. mem for DDR3
Port Name | Direction | Description |
---|---|---|
mem_ck | Output | CK clock |
mem_ck_n | Output | CK clock (negative leg) |
mem_a | Output | Address |
mem_ba | Output | Bank address |
mem_cke | Output | Clock enable |
mem_cs_n | Output | Chip select |
mem_rm | Output | Rank multiplication for LRDIMM. Typically, mem_rm[0] and mem_rm[1] connect to CS2# and CS3# of the memory buffer of all LRDIMM slots. |
mem_odt | Output | On-die termination |
mem_ras_n | Output | RAS command |
mem_cas_n | Output | CAS command |
mem_we_n | Output | WE command |
mem_reset_n | Output | Asynchronous reset |
mem_par | Output | Command and address parity |
mem_dm | Output | Write data mask |
mem_dq | Bidirectional | Read/write data |
mem_dqs | Bidirectional | Data strobe |
mem_dqs_n | Bidirectional | Data strobe (negative leg) |
mem_alert_n | Input | Alert flag |
4.1.1.11. status for DDR3
Port Name | Direction | Description |
---|---|---|
local_cal_success | Output | When high, indicates that PHY calibration was successful |
local_cal_fail | Output | When high, indicates that PHY calibration failed |
4.1.1.12. afi_reset_n for DDR3
Port Name | Direction | Description |
---|---|---|
afi_reset_n | Output | Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion |
4.1.1.13. afi_clk for DDR3
Port Name | Direction | Description |
---|---|---|
afi_clk | Output | Clock for the Altera PHY Interface (AFI) |
4.1.1.14. afi_half_clk for DDR3
Port Name | Direction | Description |
---|---|---|
afi_half_clk | Output | Clock running at half the frequency of the AFI clock afi_clk |
4.1.1.15. afi for DDR3
Port Name | Direction | Description |
---|---|---|
afi_cal_success | Output | Signals calibration successful completion |
afi_cal_fail | Output | Signals calibration failure |
afi_cal_req | Input | When asserted, the interface is recalibrated |
afi_rlat | Output | Latency in afi_clk cycles between read command and read data valid |
afi_wlat | Output | Latency in afi_clk cycles between write command and write data valid |
afi_addr | Input | Address |
afi_ba | Input | Bank address |
afi_cke | Input | Clock enable |
afi_cs_n | Input | Chip select |
afi_rm | Input | Rank multiplication for LRDIMM |
afi_odt | Input | On-die termination |
afi_ras_n | Input | RAS command |
afi_cas_n | Input | CAS command |
afi_we_n | Input | WE command |
afi_rst_n | Input | Asynchronous reset |
afi_dm | Input | Write data mask |
afi_dqs_burst | Input | Asserted by the controller to enable the output DQS signal |
afi_wdata_valid | Input | Asserted by the controller to indicate that afi_wdata contains valid write data |
afi_wdata | Input | Write data |
afi_rdata_en_full | Input | Asserted by the controller to indicate the amount of relevant read data expected |
afi_rdata | Output | Read data |
afi_rdata_valid | Output | Asserted by the PHY to indicate that afi_rdata contains valid read data |
afi_rrank | Input | Asserted by the controller to indicate which rank is being read from, to control shadow register switching |
afi_wrank | Input | Asserted by the controller to indicate which rank is being written to, to control shadow register switching |
4.1.1.16. emif_usr_reset_n for DDR3
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion |
4.1.1.17. emif_usr_clk for DDR3
Port Name | Direction | Description |
---|---|---|
emif_usr_clk | Output | User clock domain |
4.1.1.18. emif_usr_reset_n_sec for DDR3
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n_sec | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion. Intended for the secondary interface in a ping-pong configuration. |
4.1.1.19. emif_usr_clk_sec for DDR3
Port Name | Direction | Description |
---|---|---|
emif_usr_clk_sec | Output | User clock domain. Intended for the secondary interface in a ping-pong configuration. |
4.1.1.20. cal_debug_reset_n for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_reset_n | Input | Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion |
4.1.1.21. cal_debug_clk for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_clk | Input | User clock domain |
4.1.1.22. cal_debug_out_reset_n for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_reset_n | Output | Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion |
4.1.1.23. cal_debug_out_clk for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_clk | Output | User clock domain |
4.1.1.24. clks_sharing_master_out for DDR3
Port Name | Direction | Description |
---|---|---|
clks_sharing_master_out | Output | This port should fanout to all the core clocks sharing slaves. |
4.1.1.25. clks_sharing_slave_in for DDR3
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_in | Input | This port should be connected to the core clocks sharing master. |
4.1.1.26. clks_sharing_slave_out for DDR3
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_out | Output | This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves. |
4.1.1.27. ctrl_amm for DDR3
Port Name | Direction | Description |
---|---|---|
amm_ready | Output | Wait-request is asserted when controller is busy |
amm_read | Input | Read request signal |
amm_write | Input | Write request signal |
amm_address | Input | Address for the read/write request |
amm_readdata | Output | Read data |
amm_writedata | Input | Write data |
amm_burstcount | Input | Number of transfers in each read/write burst |
amm_byteenable | Input | Byte-enable for write data |
amm_beginbursttransfer | Input | Indicates when a burst is starting |
amm_readdatavalid | Output | Indicates whether read data is valid |
4.1.1.28. ctrl_auto_precharge for DDR3
Port Name | Direction | Description |
---|---|---|
ctrl_auto_precharge_req | Input | When asserted high along with a read or write request to the memory controller, indicates that the controller should close the currently opened page after the read or write burst. |
4.1.1.29. ctrl_user_priority for DDR3
Port Name | Direction | Description |
---|---|---|
ctrl_user_priority_hi | Input | When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests. |
4.1.1.30. ctrl_ecc_user_interrupt for DDR3
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_user_interrupt | Output | Controller ECC user interrupt signal to determine whether there is a bit error |
4.1.1.31. ctrl_ecc_readdataerror for DDR3
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_readdataerror | Output | Signal is asserted high by the controller ECC logic to indicate that the read data has an uncorrectable error. The signal has the same timing as the read data valid signal of the Controller Avalon Memory-Mapped interface. |
4.1.1.32. ctrl_ecc_status for DDR3
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_sts_intr | Output | ECC interrupt status - '1' indicates interrupt occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_sbe_error | Output | '1' indicates SBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_dbe_error | Output | '1' indicates DBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped | Output | Correction command dropped status, '1' indicates correction command dropped; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_sbe_count | Output | Number of times SBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_dbe_count | Output | Number of times DBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped_count | Output | Number of times correction command dropped; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_err_addr | Output | Address of the most recent SBE or DBE; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped_addr | Output | Address of the most recent correction command dropped; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
4.1.1.33. ctrl_mmr_slave for DDR3
Port Name | Direction | Description |
---|---|---|
mmr_slave_waitrequest | Output | Wait-request is asserted when controller MMR interface is busy |
mmr_slave_read | Input | MMR read request signal |
mmr_slave_write | Input | MMR write request signal |
mmr_slave_address | Input | Word address for MMR interface of memory controller |
mmr_slave_readdata | Output | MMR read data |
mmr_slave_writedata | Input | MMR write data |
mmr_slave_burstcount | Input | Number of transfers in each read/write burst |
mmr_slave_beginbursttransfer | Input | Indicates when a burst is starting |
mmr_slave_readdatavalid | Output | Indicates whether MMR read data is valid |
4.1.1.34. hps_emif for DDR3
Port Name | Direction | Description |
---|---|---|
hps_to_emif | Input | Signals coming from Hard Processor Subsystem to the memory interface |
emif_to_hps | Output | Signals going to Hard Processor Subsystem from the memory interface |
hps_to_emif_gp | Input | Signals coming from Hard Processor Subsystem GPIO to the memory interface |
emif_to_hps_gp | Output | Signals going to Hard Processor Subsystem GPIO from the memory interface |
4.1.1.35. cal_debug for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_waitrequest | Output | Wait-request is asserted when controller is busy |
cal_debug_read | Input | Read request signal |
cal_debug_write | Input | Write request signal |
cal_debug_addr | Input | Address for the read/write request |
cal_debug_read_data | Output | Read data |
cal_debug_write_data | Input | Write data |
cal_debug_byteenable | Input | Byte-enable for write data |
cal_debug_read_data_valid | Output | Indicates whether read data is valid |
4.1.1.36. cal_debug_out for DDR3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_waitrequest | Input | Wait-request is asserted when controller is busy |
cal_debug_out_read | Output | Read request signal |
cal_debug_out_write | Output | Write request signal |
cal_debug_out_addr | Output | Address for the read/write request |
cal_debug_out_read_data | Input | Read data |
cal_debug_out_write_data | Output | Write data |
cal_debug_out_byteenable | Output | Byte-enable for write data |
cal_debug_out_read_data_valid | Input | Indicates whether read data is valid |
4.1.2. Intel Stratix 10 EMIF IP Interfaces for DDR4
Interface Name | Interface Type | Description |
---|---|---|
local_reset_req | Conduit | Local reset request. Output signal from local_reset_combiner |
local_reset_status | Conduit | Local reset status. Input signal to the local_reset_combiner |
pll_ref_clk | Clock Input | PLL reference clock input |
pll_locked | Conduit | PLL locked signal |
pll_extra_clk_0 | Clock Output | Additional core clock 0 |
pll_extra_clk_1 | Clock Output | Additional core clock 1 |
pll_extra_clk_2 | Clock Output | Additional core clock 2 |
pll_extra_clk_3 | Clock Output | Additional core clock 3 |
ac_parity_err | Output | PORT_AC_PARITY_STATE_DESC |
oct | Conduit | On-Chip Termination (OCT) interface |
mem | Conduit | Interface between FPGA and external memory |
status | Conduit | PHY calibration status interface |
afi_reset_n | Reset Output | AFI reset interface |
afi_clk | Clock Output | AFI clock interface |
afi_half_clk | Clock Output | AFI half-rate clock interface |
afi | Conduit | Altera PHY Interface (AFI) |
emif_usr_reset_n | Reset Output | User clock domain reset interface |
emif_usr_clk | Clock Output | User clock interface |
emif_usr_reset_n_sec | Reset Output | User clock domain reset interface (for the secondary interface in ping-pong configuration) |
emif_usr_clk_sec | Clock Output | User clock interface (for the secondary interface in ping-pong configuration) |
cal_debug_reset_n | Reset Input | User calibration debug clock domain reset interface |
cal_debug_clk | Clock Input | User calibration debug clock interface |
cal_debug_out_reset_n | Reset Output | User calibration debug clock domain reset interface |
cal_debug_out_clk | Clock Output | User calibration debug clock interface |
clks_sharing_master_out | Conduit | Core clocks sharing master interface |
clks_sharing_slave_in | Conduit | Core clocks sharing slave input interface |
clks_sharing_slave_out | Conduit | Core clocks sharing slave output interface |
ctrl_amm | Avalon Memory-Mapped Slave | Controller Avalon Memory-Mapped interface |
ctrl_auto_precharge | Conduit | Controller auto-precharge interface |
ctrl_user_priority | Conduit | Controller user-requested priority interface |
ctrl_ecc_user_interrupt | Conduit | Controller ECC user interrupt interface |
ctrl_ecc_readdataerror | Conduit | Controller ECC read data error indication interface |
ctrl_ecc_status | Conduit | Controller ECC status interface |
ctrl_mmr_slave | Avalon Memory-Mapped Slave | Controller MMR slave interface |
hps_emif | Conduit | Conduit between Hard Processor Subsystem and memory interface |
cal_debug | Avalon Memory-Mapped Slave | Calibration debug interface |
cal_debug_out | Avalon Memory-Mapped Master | Calibration debug interface |
4.1.2.1. local_reset_req for DDR4
Port Name | Direction | Description |
---|---|---|
local_reset_req | Input | Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
4.1.2.2. local_reset_status for DDR4
Port Name | Direction | Description |
---|---|---|
local_reset_done | Output | Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. |
4.1.2.3. pll_ref_clk for DDR4
Port Name | Direction | Description |
---|---|---|
pll_ref_clk | Input | PLL reference clock input |
4.1.2.4. pll_locked for DDR4
Port Name | Direction | Description |
---|---|---|
pll_locked | Output | PLL lock signal to indicate whether the PLL has locked |
4.1.2.5. pll_extra_clk_0 for DDR4
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_0 | Output | PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.2.6. pll_extra_clk_1 for DDR4
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_1 | Output | PLL extra core clock signal output 1. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.2.7. pll_extra_clk_2 for DDR4
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_2 | Output | PLL extra core clock signal output 2. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.2.8. pll_extra_clk_3 for DDR4
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_3 | Output | PLL extra core clock signal output 3. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.2.9. ac_parity_err for DDR4
Port Name | Direction | Description |
---|---|---|
ac_parity_err | Output | PORT_AC_PARITY_STATE_DESC |
4.1.2.10. oct for DDR4
Port Name | Direction | Description |
---|---|---|
oct_rzqin | Input | Calibrated On-Chip Termination (OCT) RZQ input pin |
4.1.2.11. mem for DDR4
Port Name | Direction | Description |
---|---|---|
mem_ck | Output | CK clock |
mem_ck_n | Output | CK clock (negative leg) |
mem_a | Output | Address. Address bit A17 is defined only for the x4 configuration of 16 Gb SDRAM. |
mem_ba | Output | Bank address |
mem_bg | Output | Bank group |
mem_cke | Output | Clock enable |
mem_cs_n | Output | Chip select |
mem_odt | Output | On-die termination |
mem_reset_n | Output | Asynchronous reset |
mem_act_n | Output | Activation command |
mem_par | Output | Command and address parity |
mem_dq | Bidirectional | Read/write data |
mem_dbi_n | Bidirectional | Acts as either the data bus inversion pin, or the data mask pin, depending on configuration. |
mem_dqs | Bidirectional | Data strobe |
mem_dqs_n | Bidirectional | Data strobe (negative leg) |
mem_alert_n | Input | Alert flag |
4.1.2.12. status for DDR4
Port Name | Direction | Description |
---|---|---|
local_cal_success | Output | When high, indicates that PHY calibration was successful |
local_cal_fail | Output | When high, indicates that PHY calibration failed |
4.1.2.13. afi_reset_n for DDR4
Port Name | Direction | Description |
---|---|---|
afi_reset_n | Output | Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion |
4.1.2.14. afi_clk for DDR4
Port Name | Direction | Description |
---|---|---|
afi_clk | Output | Clock for the Altera PHY Interface (AFI) |
4.1.2.15. afi_half_clk for DDR4
Port Name | Direction | Description |
---|---|---|
afi_half_clk | Output | Clock running at half the frequency of the AFI clock afi_clk |
4.1.2.16. afi for DDR4
Port Name | Direction | Description |
---|---|---|
afi_cal_success | Output | Signals calibration successful completion |
afi_cal_fail | Output | Signals calibration failure |
afi_cal_req | Input | When asserted, the interface is recalibrated |
afi_rlat | Output | Latency in afi_clk cycles between read command and read data valid |
afi_wlat | Output | Latency in afi_clk cycles between write command and write data valid |
afi_addr | Input | Address |
afi_ba | Input | Bank address |
afi_bg | Input | Bank group |
afi_cke | Input | Clock enable |
afi_cs_n | Input | Chip select |
afi_odt | Input | On-die termination |
afi_rst_n | Input | Asynchronous reset |
afi_act_n | Input | Activation command |
afi_par | Input | Command and address parity |
afi_dm_n | Input | Write data mask |
afi_dqs_burst | Input | Asserted by the controller to enable the output DQS signal |
afi_wdata_valid | Input | Asserted by the controller to indicate that afi_wdata contains valid write data |
afi_wdata | Input | Write data |
afi_rdata_en_full | Input | Asserted by the controller to indicate the amount of relevant read data expected |
afi_rdata | Output | Read data |
afi_rdata_valid | Output | Asserted by the PHY to indicate that afi_rdata contains valid read data |
afi_rrank | Input | Asserted by the controller to indicate which rank is being read from, to control shadow register switching |
afi_wrank | Input | Asserted by the controller to indicate which rank is being written to, to control shadow register switching |
4.1.2.17. emif_usr_reset_n for DDR4
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion |
4.1.2.18. emif_usr_clk for DDR4
Port Name | Direction | Description |
---|---|---|
emif_usr_clk | Output | User clock domain |
4.1.2.19. emif_usr_reset_n_sec for DDR4
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n_sec | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion. Intended for the secondary interface in a ping-pong configuration. |
4.1.2.20. emif_usr_clk_sec for DDR4
Port Name | Direction | Description |
---|---|---|
emif_usr_clk_sec | Output | User clock domain. Intended for the secondary interface in a ping-pong configuration. |
4.1.2.21. cal_debug_reset_n for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_reset_n | Input | Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion |
4.1.2.22. cal_debug_clk for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_clk | Input | User clock domain |
4.1.2.23. cal_debug_out_reset_n for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_out_reset_n | Output | Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion |
4.1.2.24. cal_debug_out_clk for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_out_clk | Output | User clock domain |
4.1.2.25. clks_sharing_master_out for DDR4
Port Name | Direction | Description |
---|---|---|
clks_sharing_master_out | Output | This port should fanout to all the core clocks sharing slaves. |
4.1.2.26. clks_sharing_slave_in for DDR4
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_in | Input | This port should be connected to the core clocks sharing master. |
4.1.2.27. clks_sharing_slave_out for DDR4
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_out | Output | This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves. |
4.1.2.28. ctrl_amm for DDR4
Port Name | Direction | Description |
---|---|---|
amm_ready | Output | Wait-request is asserted when controller is busy |
amm_read | Input | Read request signal |
amm_write | Input | Write request signal |
amm_address | Input | Address for the read/write request |
amm_readdata | Output | Read data |
amm_writedata | Input | Write data |
amm_burstcount | Input | Number of transfers in each read/write burst |
amm_byteenable | Input | Byte-enable for write data |
amm_beginbursttransfer | Input | Indicates when a burst is starting |
amm_readdatavalid | Output | Indicates whether read data is valid |
4.1.2.29. ctrl_auto_precharge for DDR4
Port Name | Direction | Description |
---|---|---|
ctrl_auto_precharge_req | Input | When asserted high along with a read or write request to the memory controller, indicates that the controller should close the currently opened page after the read or write burst. |
4.1.2.30. ctrl_user_priority for DDR4
Port Name | Direction | Description |
---|---|---|
ctrl_user_priority_hi | Input | When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests. |
4.1.2.31. ctrl_ecc_user_interrupt for DDR4
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_user_interrupt | Output | Controller ECC user interrupt signal to determine whether there is a bit error |
4.1.2.32. ctrl_ecc_readdataerror for DDR4
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_readdataerror | Output | Signal is asserted high by the controller ECC logic to indicate that the read data has an uncorrectable error. The signal has the same timing as the read data valid signal of the Controller Avalon Memory-Mapped interface. |
4.1.2.33. ctrl_ecc_status for DDR4
Port Name | Direction | Description |
---|---|---|
ctrl_ecc_sts_intr | Output | ECC interrupt status - '1' indicates interrupt occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_sbe_error | Output | '1' indicates SBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_dbe_error | Output | '1' indicates DBE occurred; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped | Output | Correction command dropped status, '1' indicates correction command dropped; in case of ping-pong PHY, status from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_sbe_count | Output | Number of times SBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_dbe_count | Output | Number of times DBE error occurred; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped_count | Output | Number of times correction command dropped; in case of ping-pong PHY, results from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_err_addr | Output | Address of the most recent SBE or DBE; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
ctrl_ecc_sts_corr_dropped_addr | Output | Address of the most recent correction command dropped; in case of ping-pong PHY, addresses from two interfaces are concatenated as a double-width port - interface 0 at LSB, interface 1 at MSB |
4.1.2.34. ctrl_mmr_slave for DDR4
Port Name | Direction | Description |
---|---|---|
mmr_slave_waitrequest | Output | Wait-request is asserted when controller MMR interface is busy |
mmr_slave_read | Input | MMR read request signal |
mmr_slave_write | Input | MMR write request signal |
mmr_slave_address | Input | Word address for MMR interface of memory controller |
mmr_slave_readdata | Output | MMR read data |
mmr_slave_writedata | Input | MMR write data |
mmr_slave_burstcount | Input | Number of transfers in each read/write burst |
mmr_slave_beginbursttransfer | Input | Indicates when a burst is starting |
mmr_slave_readdatavalid | Output | Indicates whether MMR read data is valid |
4.1.2.35. hps_emif for DDR4
Port Name | Direction | Description |
---|---|---|
hps_to_emif | Input | Signals coming from Hard Processor Subsystem to the memory interface |
emif_to_hps | Output | Signals going to Hard Processor Subsystem from the memory interface |
hps_to_emif_gp | Input | Signals coming from Hard Processor Subsystem GPIO to the memory interface |
emif_to_hps_gp | Output | Signals going to Hard Processor Subsystem GPIO from the memory interface |
4.1.2.36. cal_debug for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_waitrequest | Output | Wait-request is asserted when controller is busy |
cal_debug_read | Input | Read request signal |
cal_debug_write | Input | Write request signal |
cal_debug_addr | Input | Address for the read/write request |
cal_debug_read_data | Output | Read data |
cal_debug_write_data | Input | Write data |
cal_debug_byteenable | Input | Byte-enable for write data |
cal_debug_read_data_valid | Output | Indicates whether read data is valid |
4.1.2.37. cal_debug_out for DDR4
Port Name | Direction | Description |
---|---|---|
cal_debug_out_waitrequest | Input | Wait-request is asserted when controller is busy |
cal_debug_out_read | Output | Read request signal |
cal_debug_out_write | Output | Write request signal |
cal_debug_out_addr | Output | Address for the read/write request |
cal_debug_out_read_data | Input | Read data |
cal_debug_out_write_data | Output | Write data |
cal_debug_out_byteenable | Output | Byte-enable for write data |
cal_debug_out_read_data_valid | Input | Indicates whether read data is valid |
4.1.3. Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme
Interface Name | Interface Type | Description |
---|---|---|
local_reset_req | Conduit | Local reset request. Output signal from local_reset_combiner |
local_reset_status | Conduit | Local reset status. Input signal to the local_reset_combiner |
pll_ref_clk | Clock Input | PLL reference clock input |
pll_locked | Conduit | PLL locked signal |
pll_extra_clk_0 | Clock Output | Additional core clock 0 |
pll_extra_clk_1 | Clock Output | Additional core clock 1 |
pll_extra_clk_2 | Clock Output | Additional core clock 2 |
pll_extra_clk_3 | Clock Output | Additional core clock 3 |
oct | Conduit | On-Chip Termination (OCT) interface |
mem | Conduit | Interface between FPGA and external memory |
status | Conduit | PHY calibration status interface |
emif_usr_reset_n | Reset Output | User clock domain reset interface |
emif_usr_clk | Clock Output | User clock interface |
cal_debug_reset_n | Reset Input | User calibration debug clock domain reset interface |
cal_debug_clk | Clock Input | User calibration debug clock interface |
cal_debug_out_reset_n | Reset Output | User calibration debug clock domain reset interface |
cal_debug_out_clk | Clock Output | User calibration debug clock interface |
clks_sharing_master_out | Conduit | Core clocks sharing master interface |
clks_sharing_slave_in | Conduit | Core clocks sharing slave input interface |
clks_sharing_slave_out | Conduit | Core clocks sharing slave output interface |
ctrl_amm | Avalon Memory-Mapped Slave | Controller Avalon Memory-Mapped interface |
cal_debug | Avalon Memory-Mapped Slave | Calibration debug interface |
cal_debug_out | Avalon Memory-Mapped Master | Calibration debug interface |
4.1.3.1. local_reset_req for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
local_reset_req | Input | Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
4.1.3.2. local_reset_status for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
local_reset_done | Output | Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. |
4.1.3.3. pll_ref_clk for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_ref_clk | Input | PLL reference clock input |
4.1.3.4. pll_locked for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_locked | Output | PLL lock signal to indicate whether the PLL has locked |
4.1.3.5. pll_extra_clk_0 for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_0 | Output | PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.3.6. pll_extra_clk_1 for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_1 | Output | PLL extra core clock signal output 1. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.3.7. pll_extra_clk_2 for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_2 | Output | PLL extra core clock signal output 2. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.3.8. pll_extra_clk_3 for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_3 | Output | PLL extra core clock signal output 3. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.3.9. oct for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
oct_rzqin | Input | Calibrated On-Chip Termination (OCT) RZQ input pin |
4.1.3.10. mem for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
mem_k | Output | K clock |
mem_k_n | Output | K clock (negative leg) |
mem_a | Output | Address |
mem_wps_n | Output | Write port select |
mem_rps_n | Output | Read port select |
mem_doff_n | Output | DLL turn off |
mem_bws_n | Output | Byte write select |
mem_d | Output | Write data |
mem_q | Input | Read data |
mem_cq | Input | Echo clock |
mem_cq_n | Input | Echo clock (negative leg) |
4.1.3.11. status for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
local_cal_success | Output | When high, indicates that PHY calibration was successful |
local_cal_fail | Output | When high, indicates that PHY calibration failed |
4.1.3.12. emif_usr_reset_n for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion |
4.1.3.13. emif_usr_clk for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
emif_usr_clk | Output | User clock domain |
4.1.3.14. cal_debug_reset_n for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_reset_n | Input | Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion |
4.1.3.15. cal_debug_clk for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_clk | Input | User clock domain |
4.1.3.16. cal_debug_out_reset_n for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_out_reset_n | Output | Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion |
4.1.3.17. cal_debug_out_clk for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_out_clk | Output | User clock domain |
4.1.3.18. clks_sharing_master_out for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
clks_sharing_master_out | Output | This port should fanout to all the core clocks sharing slaves. |
4.1.3.19. clks_sharing_slave_in for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_in | Input | This port should be connected to the core clocks sharing master. |
4.1.3.20. clks_sharing_slave_out for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_out | Output | This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves. |
4.1.3.21. ctrl_amm for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
amm_ready | Output | Wait-request is asserted when controller is busy |
amm_read | Input | Read request signal |
amm_write | Input | Write request signal |
amm_address | Input | Address for the read/write request |
amm_readdata | Output | Read data |
amm_writedata | Input | Write data |
amm_burstcount | Input | Number of transfers in each read/write burst |
amm_byteenable | Input | Byte-enable for write data |
amm_beginbursttransfer | Input | Indicates when a burst is starting |
amm_readdatavalid | Output | Indicates whether read data is valid |
4.1.3.22. cal_debug for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_waitrequest | Output | Wait-request is asserted when controller is busy |
cal_debug_read | Input | Read request signal |
cal_debug_write | Input | Write request signal |
cal_debug_addr | Input | Address for the read/write request |
cal_debug_read_data | Output | Read data |
cal_debug_write_data | Input | Write data |
cal_debug_byteenable | Input | Byte-enable for write data |
cal_debug_read_data_valid | Output | Indicates whether read data is valid |
4.1.3.23. cal_debug_out for QDR II/II+/II+ Xtreme
Port Name | Direction | Description |
---|---|---|
cal_debug_out_waitrequest | Input | Wait-request is asserted when controller is busy |
cal_debug_out_read | Output | Read request signal |
cal_debug_out_write | Output | Write request signal |
cal_debug_out_addr | Output | Address for the read/write request |
cal_debug_out_read_data | Input | Read data |
cal_debug_out_write_data | Output | Write data |
cal_debug_out_byteenable | Output | Byte-enable for write data |
cal_debug_out_read_data_valid | Input | Indicates whether read data is valid |
4.1.4. Intel Stratix 10 EMIF IP Interfaces for QDR-IV
Interface Name | Interface Type | Description |
---|---|---|
local_reset_req | Conduit | Local reset request. Output signal from local_reset_combiner |
local_reset_status | Conduit | Local reset status. Input signal to the local_reset_combiner |
pll_ref_clk | Clock Input | PLL reference clock input |
pll_locked | Conduit | PLL locked signal |
pll_extra_clk_0 | Clock Output | Additional core clock 0 |
pll_extra_clk_1 | Clock Output | Additional core clock 1 |
pll_extra_clk_2 | Clock Output | Additional core clock 2 |
pll_extra_clk_3 | Clock Output | Additional core clock 3 |
oct | Conduit | On-Chip Termination (OCT) interface |
mem | Conduit | Interface between FPGA and external memory |
status | Conduit | PHY calibration status interface |
afi_reset_n | Reset Output | AFI reset interface |
afi_clk | Clock Output | AFI clock interface |
afi_half_clk | Clock Output | AFI half-rate clock interface |
afi | Conduit | Altera PHY Interface (AFI) |
emif_usr_reset_n | Reset Output | User clock domain reset interface |
emif_usr_clk | Clock Output | User clock interface |
cal_debug_reset_n | Reset Input | User calibration debug clock domain reset interface |
cal_debug_clk | Clock Input | User calibration debug clock interface |
cal_debug_out_reset_n | Reset Output | User calibration debug clock domain reset interface |
cal_debug_out_clk | Clock Output | User calibration debug clock interface |
clks_sharing_master_out | Conduit | Core clocks sharing master interface |
clks_sharing_slave_in | Conduit | Core clocks sharing slave input interface |
clks_sharing_slave_out | Conduit | Core clocks sharing slave output interface |
ctrl_amm | Avalon Memory-Mapped Slave | Controller Avalon Memory-Mapped interface |
cal_debug | Avalon Memory-Mapped Slave | Calibration debug interface |
cal_debug_out | Avalon Memory-Mapped Master | Calibration debug interface |
4.1.4.1. local_reset_req for QDR-IV
Port Name | Direction | Description |
---|---|---|
local_reset_req | Input | Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
4.1.4.2. local_reset_status for QDR-IV
Port Name | Direction | Description |
---|---|---|
local_reset_done | Output | Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. |
4.1.4.3. pll_ref_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_ref_clk | Input | PLL reference clock input |
4.1.4.4. pll_locked for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_locked | Output | PLL lock signal to indicate whether the PLL has locked |
4.1.4.5. pll_extra_clk_0 for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_0 | Output | PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.4.6. pll_extra_clk_1 for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_1 | Output | PLL extra core clock signal output 1. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.4.7. pll_extra_clk_2 for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_2 | Output | PLL extra core clock signal output 2. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.4.8. pll_extra_clk_3 for QDR-IV
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_3 | Output | PLL extra core clock signal output 3. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.4.9. oct for QDR-IV
Port Name | Direction | Description |
---|---|---|
oct_rzqin | Input | Calibrated On-Chip Termination (OCT) RZQ input pin |
4.1.4.10. mem for QDR-IV
Port Name | Direction | Description |
---|---|---|
mem_ck | Output | CK clock |
mem_ck_n | Output | CK clock (negative leg) |
mem_dka | Output | DK clock for port A |
mem_dka_n | Output | DK clock for port A (negative leg) |
mem_dkb | Output | DK clock for port B |
mem_dkb_n | Output | DK clock for port B (negative leg) |
mem_a | Output | Address |
mem_reset_n | Output | Asynchronous reset |
mem_lda_n | Output | Synchronous load for port A |
mem_ldb_n | Output | Synchronous load for port B |
mem_rwa_n | Output | Synchronous read/write for port A |
mem_rwb_n | Output | Synchronous read/write for port B |
mem_lbk0_n | Output | Loopback mode |
mem_lbk1_n | Output | Loopback mode |
mem_cfg_n | Output | Configuration bit |
mem_ap | Output | Address parity |
mem_ainv | Output | Address inversion |
mem_dqa | Bidirectional | Read/write data for port A |
mem_dqb | Bidirectional | Read/write data for port B |
mem_dinva | Bidirectional | Read/write data inversion for port A |
mem_dinvb | Bidirectional | Read/write data inversion for port B |
mem_qka | Input | Read data clock for port A |
mem_qka_n | Input | Read data clock for port A (negative leg) |
mem_qkb | Input | Read data clock for port B |
mem_qkb_n | Input | Read data clock for port B (negative leg) |
mem_pe_n | Input | Address parity error flag |
4.1.4.11. status for QDR-IV
Port Name | Direction | Description |
---|---|---|
local_cal_success | Output | When high, indicates that PHY calibration was successful |
local_cal_fail | Output | When high, indicates that PHY calibration failed |
4.1.4.12. afi_reset_n for QDR-IV
Port Name | Direction | Description |
---|---|---|
afi_reset_n | Output | Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion |
4.1.4.13. afi_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
afi_clk | Output | Clock for the Altera PHY Interface (AFI) |
4.1.4.14. afi_half_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
afi_half_clk | Output | Clock running at half the frequency of the AFI clock afi_clk |
4.1.4.15. afi for QDR-IV
Port Name | Direction | Description |
---|---|---|
afi_ld_n | Input | Synchronous load for port A and B |
afi_rw_n | Input | Synchronous read/write for port A and B |
afi_lbk0_n | Input | Loopback mode |
afi_lbk1_n | Input | Loopback mode |
afi_cfg_n | Input | Configuration bit |
afi_ap | Input | Address parity |
afi_ainv | Input | Address inversion |
afi_rdata_dinv | Output | Data inversion for read data |
afi_wdata_dinv | Input | Data inversion for write data |
afi_pe_n | Output | Address parity error flag |
4.1.4.16. emif_usr_reset_n for QDR-IV
Port Name | Direction | Description |
---|---|---|
emif_usr_reset_n | Output | Reset for the user clock domain. Asynchronous assertion and synchronous deassertion |
4.1.4.17. emif_usr_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
emif_usr_clk | Output | User clock domain |
4.1.4.18. cal_debug_reset_n for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_reset_n | Input | Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion |
4.1.4.19. cal_debug_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_clk | Input | User clock domain |
4.1.4.20. cal_debug_out_reset_n for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_out_reset_n | Output | Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion |
4.1.4.21. cal_debug_out_clk for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_out_clk | Output | User clock domain |
4.1.4.22. clks_sharing_master_out for QDR-IV
Port Name | Direction | Description |
---|---|---|
clks_sharing_master_out | Output | This port should fanout to all the core clocks sharing slaves. |
4.1.4.23. clks_sharing_slave_in for QDR-IV
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_in | Input | This port should be connected to the core clocks sharing master. |
4.1.4.24. clks_sharing_slave_out for QDR-IV
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_out | Output | This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves. |
4.1.4.25. ctrl_amm for QDR-IV
Port Name | Direction | Description |
---|---|---|
amm_ready | Output | Wait-request is asserted when controller is busy |
amm_read | Input | Read request signal |
amm_write | Input | Write request signal |
amm_address | Input | Address for the read/write request |
amm_readdata | Output | Read data |
amm_writedata | Input | Write data |
amm_burstcount | Input | Number of transfers in each read/write burst |
amm_beginbursttransfer | Input | Indicates when a burst is starting |
amm_readdatavalid | Output | Indicates whether read data is valid |
4.1.4.26. cal_debug for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_waitrequest | Output | Wait-request is asserted when controller is busy |
cal_debug_read | Input | Read request signal |
cal_debug_write | Input | Write request signal |
cal_debug_addr | Input | Address for the read/write request |
cal_debug_read_data | Output | Read data |
cal_debug_write_data | Input | Write data |
cal_debug_byteenable | Input | Byte-enable for write data |
cal_debug_read_data_valid | Output | Indicates whether read data is valid |
4.1.4.27. cal_debug_out for QDR-IV
Port Name | Direction | Description |
---|---|---|
cal_debug_out_waitrequest | Input | Wait-request is asserted when controller is busy |
cal_debug_out_read | Output | Read request signal |
cal_debug_out_write | Output | Write request signal |
cal_debug_out_addr | Output | Address for the read/write request |
cal_debug_out_read_data | Input | Read data |
cal_debug_out_write_data | Output | Write data |
cal_debug_out_byteenable | Output | Byte-enable for write data |
cal_debug_out_read_data_valid | Input | Indicates whether read data is valid |
4.1.5. Intel Stratix 10 EMIF IP Interfaces for RLDRAM 3
Interface Name | Interface Type | Description |
---|---|---|
local_reset_req | Conduit | Local reset request. Output signal from local_reset_combiner |
local_reset_status | Conduit | Local reset status. Input signal to the local_reset_combiner |
pll_ref_clk | Clock Input | PLL reference clock input |
pll_locked | Conduit | PLL locked signal |
pll_extra_clk_0 | Clock Output | Additional core clock 0 |
pll_extra_clk_1 | Clock Output | Additional core clock 1 |
pll_extra_clk_2 | Clock Output | Additional core clock 2 |
pll_extra_clk_3 | Clock Output | Additional core clock 3 |
oct | Conduit | On-Chip Termination (OCT) interface |
mem | Conduit | Interface between FPGA and external memory |
status | Conduit | PHY calibration status interface |
afi_reset_n | Reset Output | AFI reset interface |
afi_clk | Clock Output | AFI clock interface |
afi_half_clk | Clock Output | AFI half-rate clock interface |
afi | Conduit | Altera PHY Interface (AFI) |
cal_debug_reset_n | Reset Input | User calibration debug clock domain reset interface |
cal_debug_clk | Clock Input | User calibration debug clock interface |
cal_debug_out_reset_n | Reset Output | User calibration debug clock domain reset interface |
cal_debug_out_clk | Clock Output | User calibration debug clock interface |
clks_sharing_master_out | Conduit | Core clocks sharing master interface |
clks_sharing_slave_in | Conduit | Core clocks sharing slave input interface |
clks_sharing_slave_out | Conduit | Core clocks sharing slave output interface |
cal_debug | Avalon Memory-Mapped Slave | Calibration debug interface |
cal_debug_out | Avalon Memory-Mapped Master | Calibration debug interface |
4.1.5.1. local_reset_req for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
local_reset_req | Input | Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. |
4.1.5.2. local_reset_status for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
local_reset_done | Output | Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. |
4.1.5.3. pll_ref_clk for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_ref_clk | Input | PLL reference clock input |
4.1.5.4. pll_locked for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_locked | Output | PLL lock signal to indicate whether the PLL has locked |
4.1.5.5. pll_extra_clk_0 for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_0 | Output | PLL extra core clock signal output 0. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.5.6. pll_extra_clk_1 for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_1 | Output | PLL extra core clock signal output 1. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.5.7. pll_extra_clk_2 for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_2 | Output | PLL extra core clock signal output 2. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.5.8. pll_extra_clk_3 for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
pll_extra_clk_3 | Output | PLL extra core clock signal output 3. This signal exists if you specify the EMIF PLL to generate additional output clock signals (up to 4) that can be used by user logic. This clock signal is asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. |
4.1.5.9. oct for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
oct_rzqin | Input | Calibrated On-Chip Termination (OCT) RZQ input pin |
4.1.5.10. mem for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
mem_ck | Output | CK clock |
mem_ck_n | Output | CK clock (negative leg) |
mem_dk | Output | DK clock |
mem_dk_n | Output | DK clock (negative leg) |
mem_a | Output | Address |
mem_ba | Output | Bank address |
mem_cs_n | Output | Chip select |
mem_rm | Output | Rank multiplication for LRDIMM. Typically, mem_rm[0] and mem_rm[1] connect to CS2# and CS3# of the memory buffer of all LRDIMM slots. |
mem_we_n | Output | WE command |
mem_reset_n | Output | Asynchronous reset |
mem_ref_n | Output | REF command |
mem_dm | Output | Write data mask |
mem_dq | Bidirectional | Read/write data |
mem_qk | Input | Read data clock |
mem_qk_n | Input | Read data clock (negative leg) |
4.1.5.11. status for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
local_cal_success | Output | When high, indicates that PHY calibration was successful |
local_cal_fail | Output | When high, indicates that PHY calibration failed |
4.1.5.12. afi_reset_n for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
afi_reset_n | Output | Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion |
4.1.5.13. afi_clk for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
afi_clk | Output | Clock for the Altera PHY Interface (AFI) |
4.1.5.14. afi_half_clk for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
afi_half_clk | Output | Clock running at half the frequency of the AFI clock afi_clk |
4.1.5.15. afi for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
afi_cal_success | Output | Signals calibration successful completion |
afi_cal_fail | Output | Signals calibration failure |
afi_cal_req | Input | When asserted, the interface is recalibrated |
afi_rlat | Output | Latency in afi_clk cycles between read command and read data valid |
afi_wlat | Output | Latency in afi_clk cycles between write command and write data valid |
afi_addr | Input | Address |
afi_ba | Input | Bank address |
afi_cs_n | Input | Chip select |
afi_we_n | Input | WE command |
afi_rst_n | Input | Asynchronous reset |
afi_ref_n | Input | REF command |
afi_dm | Input | Write data mask |
afi_wdata_valid | Input | Asserted by the controller to indicate that afi_wdata contains valid write data |
afi_wdata | Input | Write data |
afi_rdata_en_full | Input | Asserted by the controller to indicate the amount of relevant read data expected |
afi_rdata | Output | Read data |
afi_rdata_valid | Output | Asserted by the PHY to indicate that afi_rdata contains valid read data |
afi_rrank | Input | Asserted by the controller to indicate which rank is being read from, to control shadow register switching |
afi_wrank | Input | Asserted by the controller to indicate which rank is being written to, to control shadow register switching |
4.1.5.16. cal_debug_reset_n for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_reset_n | Input | Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion |
4.1.5.17. cal_debug_clk for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_clk | Input | User clock domain |
4.1.5.18. cal_debug_out_reset_n for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_reset_n | Output | Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion |
4.1.5.19. cal_debug_out_clk for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_clk | Output | User clock domain |
4.1.5.20. clks_sharing_master_out for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
clks_sharing_master_out | Output | This port should fanout to all the core clocks sharing slaves. |
4.1.5.21. clks_sharing_slave_in for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_in | Input | This port should be connected to the core clocks sharing master. |
4.1.5.22. clks_sharing_slave_out for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
clks_sharing_slave_out | Output | This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves. |
4.1.5.23. cal_debug for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_waitrequest | Output | Wait-request is asserted when controller is busy |
cal_debug_read | Input | Read request signal |
cal_debug_write | Input | Write request signal |
cal_debug_addr | Input | Address for the read/write request |
cal_debug_read_data | Output | Read data |
cal_debug_write_data | Input | Write data |
cal_debug_byteenable | Input | Byte-enable for write data |
cal_debug_read_data_valid | Output | Indicates whether read data is valid |
4.1.5.24. cal_debug_out for RLDRAM 3
Port Name | Direction | Description |
---|---|---|
cal_debug_out_waitrequest | Input | Wait-request is asserted when controller is busy |
cal_debug_out_read | Output | Read request signal |
cal_debug_out_write | Output | Write request signal |
cal_debug_out_addr | Output | Address for the read/write request |
cal_debug_out_read_data | Input | Read data |
cal_debug_out_write_data | Output | Write data |
cal_debug_out_byteenable | Output | Byte-enable for write data |
cal_debug_out_read_data_valid | Input | Indicates whether read data is valid |
4.2. AFI Signals
In each table, the Direction column denotes the direction of the signal relative to the PHY. For example, a signal defined as an output passes out of the PHY to the controller. The AFI specification does not include any bidirectional signals.
4.2.1. AFI Clock and Reset Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_clk |
Output |
1 |
Clock with which all data exchanged on the AFI bus is synchronized. In general, this clock is referred to as full-rate, half-rate, or quarter-rate, depending on the ratio between the frequency of this clock and the frequency of the memory device clock. |
afi_half_clk |
Output |
1 |
Clock signal that runs at half the speed of the afi_clk. The controller uses this signal when the half-rate bridge feature is in use. This signal is optional. |
afi_reset_n |
Output |
1 |
Asynchronous reset output signal. You must synchronize this signal to the clock domain in which you use it. |
4.2.2. AFI Address and Command Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_addr |
Input |
AFI_ADDR_WIDTH |
Address. |
afi_bg |
Input |
AFI_BANKGROUP_WIDTH |
Bank group (DDR4 only). |
afi_ba |
Input |
AFI_BANKADDR_WIDTH |
Bank address. |
afi_cke |
Input |
AFI_CLK_EN_WIDTH |
Clock enable. |
afi_cs_n |
Input |
AFI_CS_WIDTH |
Chip select signal. (The number of chip selects may not match the number of ranks; for example, RDIMMs and LRDIMMs require a minimum of 2 chip select signals for both single-rank and dual-rank configurations. Consult your memory device data sheet for information about chip select signal width.) |
afi_ras_n |
Input |
AFI_CONTROL_WIDTH |
RAS# (for DDR3 memory devices.) |
afi_we_n |
Input |
AFI_CONTROL_WIDTH |
WE# (for DDR3 memory devices.) |
afi_rw_n |
Input |
AFI_CONTROL_WIDTH * 2 |
RWA/B# (QDR-IV). |
afi_cas_n |
Input |
AFI_CONTROL_WIDTH |
CAS# (for DDR3 memory devices.) |
afi_act_n |
Input |
AFI_CONTROL_WIDTH |
ACT# (DDR4). |
afi_rst_n |
Input |
AFI_CONTROL_WIDTH |
RESET# (for DDR3 and DDR4 memory devices.) |
afi_odt |
Input |
AFI_CLK_EN_WIDTH |
On-die termination signal for DDR3 memory devices. (Do not confuse this memory device signal with the FPGA’s internal on-chip termination signal.) |
afi_par |
Input |
AFI_CS_WIDTH |
Address and command parity input. (DDR4) Address parity input. (QDR-IV) |
afi_ainv |
Input |
AFI_CONTROL_WIDTH |
Address inversion. (QDR-IV) |
afi_mem_clk_disable |
Input |
AFI_CLK_PAIR_COUNT |
When this signal is asserted, mem_clk and mem_clk_n are disabled. This signal is used in low-power mode. |
afi_wps_n |
Output |
AFI_CS_WIDTH |
WPS (for QDR II/II+ memory devices.) |
afi_rps_n |
Output |
AFI_CS_WIDTH |
RPS (for QDR II/II+ memory devices.) |
4.2.3. AFI Write Data Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_dqs_burst |
Input |
AFI_RATE_RATIO |
Controls the enable on the strobe (DQS) pins for DDR3 memory devices. When this signal is asserted, mem_dqs and mem_dqsn are driven. This signal must be asserted before afi_wdata_valid to implement the write preamble, and must be driven for the correct duration to generate a correctly timed mem_dqs signal. |
afi_wdata_valid |
Input |
AFI_RATE_RATIO |
Write data valid signal. This signal controls the output enable on the data and data mask pins. |
afi_wdata |
Input |
AFI_DQ_WIDTH |
Write data signal to send to the memory device at double-data rate. This signal controls the PHY’s mem_dq output. |
afi_dm |
Input |
AFI_DM_WIDTH |
Data mask. This signal controls the PHY’s mem_dm signal for DDR3 memory devices. Also directly controls the PHY's mem_dbi signal for DDR4. The mem_dm and mem_dbi features share the same port on the memory device. |
afi_bws_n |
Input |
AFI_DM_WIDTH |
Data mask. This signal controls the PHY’s mem_bws_n signal for QDR II/II+ memory devices. |
afi_dinv |
Input |
AFI_WRITE_DQS_WIDTH * 2 |
Data inversion. It directly controls the PHY's mem_dinva/b signal for QDR-IV devices. |
4.2.4. AFI Read Data Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_rdata_en_full |
Input |
AFI_RATE_RATIO |
Read data enable full. Indicates that the memory controller is currently performing a read operation. This signal is held high for the entire read burst.If this signal is aligned to even clock cycles, it is possible to use 1-bit even in half-rate mode (i.e., AFI_RATE=2). |
afi_rdata |
Output |
AFI_DQ_WIDTH |
Read data from the memory device. This data is considered valid only when afi_rdata_valid is asserted by the PHY. |
afi_rdata_valid |
Output |
AFI_RATE_RATIO |
Read data valid. When asserted, this signal indicates that the afi_rdata bus is valid.If this signal is aligned to even clock cycles, it is possible to use 1-bit even in half-rate mode (i.e., AFI_RATE=2). |
4.2.5. AFI Calibration Status Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_cal_success |
Output |
1 |
Asserted to indicate that calibration has completed successfully. |
afi_cal_fail |
Output |
1 |
Asserted to indicate that calibration has failed. |
afi_cal_req |
Input |
1 |
Effectively a synchronous reset for the sequencer. When this signal is asserted, the sequencer returns to the reset state; when this signal is released, a new calibration sequence begins. |
afi_wlat |
Output |
AFI_WLAT_WIDTH |
The required write latency in afi_clk cycles, between address/command and write data being issued at the PHY/controller interface. The afi_wlat value can be different for different groups; each group’s write latency can range from 0 to 63. If write latency is the same for all groups, only the lowest 6 bits are required. |
afi_rlat (1) |
Output |
AFI_RLAT_WIDTH |
The required read latency in afi_clk cycles between address/command and read data being returned to the PHY/controller interface. Values can range from 0 to 63. |
Note to Table:
|
4.2.6. AFI Shadow Register Management Signals
During a rank-to-rank switch, the correct set of calibrated settings is restored just in time to optimize the data valid window. The PHY relies on additional AFI signals to control which set of shadow registers to activate.
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_wrank |
Input |
AFI_WRANK_WIDTH |
Signal from controller specifying which rank the write data is going to. The signal timing is identical to that of afi_dqs_burst. That is, afi_wrank must be asserted at the same time and must last the same duration as the afi_dqs_burst signal. |
afi_rrank |
Output |
AFI_RRANK_WIDTH |
Signal from controller specifying which rank is being read. The signal must be asserted at the same time as the afi_rdata_en signal when issuing a read command, but unlike afi_rdata_en, afi_rrank is stateful. That is, once asserted, the signal value must remain unchanged until the controller issues a new read command to a different rank. |
Both the afi_wrank and afi_rrank signals encode the rank being accessed using the one-hot scheme (e.g. in a quad-rank interface, 0001, 0010, 0100, 1000 refer to the 1st, 2nd, 3rd, 4th rank respectively). The ordering within the bus is the same as other AFI signals. Specifically the bus is ordered by time slots, for example:
Half-rate afi_w/rrank = {T1, T0}
Quarter-rate afi_w/rrank = {T3, T2, T1, T0}
Where Tx is a number of rank-bit words that one-hot encodes the rank being accessed at the y th full-rate cycle.
Additional Requirements for Shadow Register Support
To ensure that the hardware has enough time to switch from one shadow register to another, the controller must satisfy the following minimum rank-to-rank-switch delays (tRTRS):
- Two read commands going to different ranks must be separated by a minimum of 3 full-rate cycles (in addition to the burst length delay needed to avoid collision of data bursts).
- Two write commands going to different rank must be separated by a minimum of 4 full-rate cycles (in addition to the burst length delay needed to avoid collision of data bursts).
The FPGA device supports a maximum of 4 sets of shadow registers, each for an independent set of timings. More than 4 ranks are supported if those ranks have four or fewer sets of independent timing. For example, the rank multiplication mode of an LRDIMM allows more than one physical rank to share a set of timing data as a single logical rank. Therefore the device can support up to 4 logical ranks, though that means more than 4 physical ranks.
4.3. AFI 4.0 Timing Diagrams
4.3.1. AFI Address and Command Timing Diagrams
The waveforms show how the AFI command phase corresponds to the memory command output. AFI command 0 corresponds to the first memory command slot, AFI command 1 corresponds to the second memory command slot, and so on.
4.3.2. AFI Write Sequence Timing Diagrams
Write sequences with wlat=0
For half rate and quarter rate, when the write command is sent on the first memory clock in a PHY clock (for example, afi_cs_n[0] = 0), that access is called aligned access; otherwise it is called unaligned access. You may use either aligned or unaligned access, or you may use both, but you must ensure that the distance between the write command and the corresponding write data are constant on the AFI interface. For example, if a command is sent on the second memory clock in a PHY clock, the write data must also start at the second memory clock in a PHY clock.
The following diagrams illustrate both aligned and unaligned access. The first three write commands are aligned accesses where they were issued on LSB of afi_command. The fourth write command is unaligned access where it was issued on a different command slot. AFI signals must be shifted accordingly, based on the command slot.
Write sequences with wlat=non-zero
The afi_wlat is a signal from the PHY. The controller must delay afi_dqs_burst, afi_wdata_valid, afi_wdata and afi_dm signals by a number of PHY clock cycles equal to afi_wlat, which is a static value determined by calibration before the PHY asserts cal_success to the controller. The following figures illustrate the cases when wlat=1. Note that wlat is in the number of PHY clocks and therefore wlat=1 equals 1, 2, and 4 memory clocks delay, respectively, on full, half and quarter rate.
DQS burst
The afi_dqs_burst signal must be asserted one or two complete memory clock cycles earlier to generate DQS preamble. DQS preamble is equal to one-half and one-quarter AFI clock cycles in half and quarter rate, respectively.
A DQS preamble of two is required in DDR4, when the write preamble is set to two clock cycles.
The following diagrams illustrate how afi_dqs_burst must be asserted in full, half, and quarter-rate configurations.
Write data sequence with DBI (DDR4 and QDRIV only)
The DDR4 write DBI feature is supported in the PHY, and when it is enabled, the PHY sends and receives the DBI signal without any controller involvement. The sequence is identical to non-DBI scenarios on the AFI interface.
Write data sequence with CRC (DDR4 only)
When the CRC feature of the PHY is enabled and used, the controller ensures at least one memory clock cycle between write commands, during which the PHY inserts the CRC data. Sending back to back write command would cause functional failure. The following figures show the legal sequences in CRC mode.
Entries marked as 0 and RESERVE must be observed by the controller; no information is allowed on those entries.
4.3.3. AFI Read Sequence Timing Diagrams
The afi_rdata_en_full signal must be asserted for the entire read burst operation. The afi_rdata_en signal need only be asserted for the intended read data.
Aligned and unaligned access for read commands is similar to write commands; however, the afi_rdata_en_full signal must be sent on the same memory clock in a PHY clock as the read command. That is, if a read command is sent on the second memory clock in a PHY clock, afi_rdata_en_full must also be asserted, starting from the second memory clock in a PHY clock.
The following figure illustrates that the second and third reads require only the first and second half of data, respectively. The first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.
In the following figure, the first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.
4.3.4. AFI Calibration Status Timing Diagram
At power-up, the PHY holds afi_cal_success and afi_cal_fail 0 until calibration is done, when it asserts afi_cal_success, indicating to controller that the PHY is ready to use and afi_wlat and afi_rlat signals have valid values.
At recalibration, the controller asserts afi_cal_req, which triggers the same sequence as at power-up, and forces recalibration of the PHY.
4.4. Intel Stratix 10 Memory Mapped Register (MMR) Tables
Register Summary
Register | Address 32-bit Bus | Bits Register Link |
---|---|---|
ctrlcfg0 | 10 | 32 |
ctrlcfg1 | 11 | 32 |
dramtiming0 | 20 | 32 |
caltiming0 | 31 | 32 |
caltiming1 | 32 | 32 |
caltiming2 | 33 | 32 |
caltiming3 | 34 | 32 |
caltiming4 | 35 | 32 |
caltiming9 | 40 | 32 |
dramaddrw | 42 | 32 |
sideband0 | 43 | 32 |
sideband1 | 44 | 32 |
sideband4 | 47 | 32 |
sideband6 | 49 | 32 |
sideband7 | 50 | 32 |
sideband9 | 52 | 32 |
sideband11 | 54 | 32 |
sideband12 | 55 | 32 |
sideband13 | 56 | 32 |
sideband14 | 57 | 32 |
dramsts | 59 | 32 |
niosreserve0 | 68 | 32 |
niosreserve1 | 69 | 32 |
sideband16 | 79 | 32 |
ecc3 | 130 | 32 |
ecc4 | 144 | 32 |
ecc5 | 145 | 32 |
ecc6 | 146 | 32 |
ecc7 | 147 | 32 |
ecc8 | 148 | 32 |
4.4.1. ctrlcfg0
address=10(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_mem_type | 3 | 0 | Indicates memory type. "0000" for DDR3 SDRAM, and "0001" for DDR4 SDRAM. | Read |
cfg_dimm_type | 6 | 4 | Indicates dimm type. | Read |
cfg_ac_pos | 8 | 7 | Indicates Command Address pin position. | Read |
Reserved | 31 | 9 | Reserved. | Read |
4.4.2. ctrlcfg1
address=11(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
Reserved | 4 | 0 | Reserved. | Read |
cfg_addr_order | 6 | 5 | Indicates the order for address interleaving. This is related to mappings between Avalon-MM address and the SDRAM address. "00" - chip, row, bank(BG, BA), column; "01" - chip, bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column. | Read |
cfg_ctrl_enable_ecc | 7 | 7 | Enable the generation and checking of ECC. | Read |
cfg_dbc0_enable_ecc | 8 | 8 | Enable the generation and checking of ECC. | Read |
cfg_dbc1_enable_ecc | 9 | 9 | Enable the generation and checking of ECC. | Read |
cfg_dbc2_enable_ecc | 10 | 10 | Enable the generation and checking of ECC. | Read |
cfg_dbc3_enable_ecc | 11 | 11 | Enable the generation and checking of ECC. | Read |
cfg_reorder_data | 12 | 12 | This bit controls whether the controller can reorder operations to optimize SDRAM bandwidth. It should generally be set to a one. | Read |
cfg_ctrl_reorder_rdata | 13 | 13 | This bit controls whether the controller needs to reorder the read return data. | Read |
cfg_dbc0_reorder_rdata | 14 | 14 | This bit controls whether the controller needs to reorder the read return data. | Read |
cfg_dbc1_reorder_rdata | 15 | 15 | This bit controls whether the controller needs to reorder the read return data. | Read |
cfg_dbc2_reorder_rdata | 16 | 16 | This bit controls whether the controller needs to reorder the read return data. | Read |
cfg_dbc3_reorder_rdata | 17 | 17 | This bit controls whether the controller needs to reorder the read return data. | Read |
cfg_reorder_read | 18 | 18 | This bit controls whether the controller can reorder read command. | Read |
cfg_starve_limit | 24 | 19 | Specifies the number of DRAM burst transactions that an individual transaction allows to reorder ahead of it before its priority is raised in the memory controller. | Read |
Reserved | 25 | 25 | Reserved. | Read |
cfg_ctrl_enable_dm | 26 | 26 | Set to 1 to enable DRAM operation if DM pins are connected. | Read |
cfg_dbc0_enable_dm | 27 | 27 | Set to 1 to enable DRAM operation if DM pins are connected. | Read |
cfg_dbc1_enable_dm | 28 | 28 | Set to 1 to enable DRAM operation if DM pins are connected. | Read |
cfg_dbc2_enable_dm | 29 | 29 | Set to 1 to enable DRAM operation if DM pins are connected. | Read |
cfg_dbc3_enable_dm | 30 | 30 | Set to 1 to enable DRAM operation if DM pins are connected. | Read |
4.4.3. dramtiming0
address=20(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_tcl | 6 | 0 | Memory read latency. | Read |
Reserved | 31 | 7 | Reserved. | Read |
4.4.4. caltiming0
address=31(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_act_to_rdwr | 5 | 0 | Activate to Read/Write command timing. | Read |
cfg_t_param_act_to_pch | 11 | 6 | Active to precharge. | Read |
cfg_t_param_act_to_act | 17 | 12 | Active to activate timing on same bank. | Read |
cfg_t_param_act_to_act_diff_bank | 23 | 18 | Active to activate timing on different banks, for DDR4 same bank group. | Read |
cfg_t_param_act_to_act_diff_bg | 29 | 24 | Active to activate timing on different bank groups, DDR4 only. | Read |
4.4.5. caltiming1
address=32(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_rd_to_rd | 5 | 0 | Read to read command timing on same bank. | Read |
cfg_t_param_rd_to_rd_diff_chip | 11 | 6 | Read to read command timing on different chips. | Read |
cfg_t_param_rd_to_rd_diff_bg | 17 | 12 | Read to read command timing on different chips. | Read |
cfg_t_param_rd_to_wr | 23 | 18 | Write to read command timing on same bank. | Read |
cfg_t_param_rd_to_wr_diff_chip | 29 | 24 | Read to write command timing on different chips | Read |
4.4.6. caltiming2
address=33(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_rd_to_wr_diff_bg | 5 | 0 | Read to write command timing on different bank groups. | Read |
cfg_t_param_rd_to_pch | 11 | 6 | Read to precharge command timing. | Read |
cfg_t_param_rd_ap_to_valid | 17 | 12 | Read command with autoprecharge to data valid timing. | Read |
cfg_t_param_wr_to_wr | 23 | 18 | Write to write command timing on same bank. | Read |
cfg_t_param_wr_to_wr_diff_chip | 29 | 24 | Write to write command timing on different chips. | Read |
4.4.7. caltiming3
address=34(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_wr_to_wr_diff_bg | 5 | 0 | Write to write command timing on different bank groups. | Read |
cfg_t_param_wr_to_rd | 11 | 6 | Write to read command timing. | Read |
cfg_t_param_wr_to_rd_diff_chip | 17 | 12 | Write to read command timing on different chips. | Read |
cfg_t_param_wr_to_rd_diff_bg | 23 | 18 | Write to read command timing on different bank groups. | Read |
cfg_t_param_wr_to_pch | 29 | 24 | Write to precharge command timing. | Read |
4.4.8. caltiming4
address=35(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_wr_ap_to_valid | 5 | 0 | Write with autoprecharge to valid command timing. | Read |
cfg_t_param_pch_to_valid | 11 | 6 | Precharge to valid command timing. | Read |
cfg_t_param_pch_all_to_valid | 17 | 12 | Precharge all to banks being ready for bank activation command. | Read |
cfg_t_param_arf_to_valid | 25 | 18 | Auto Refresh to valid DRAM command window. | Read |
cfg_t_param_pdn_to_valid | 31 | 26 | Power down to valid bank command window. | Read |
4.4.9. caltiming9
address=40(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_t_param_4_act_to_act | 7 | 0 | The four-activate window timing parameter. | Read |
4.4.10. dramaddrw
address=42(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_col_addr_width | 4 | 0 | The number of column address bits for the memory devices in your memory interface. | Read |
cfg_row_addr_width | 9 | 5 | The number of row address bits for the memory devices in your memory interface. | Read |
cfg_bank_addr_width | 13 | 10 | The number of bank address bits for the memory devices in your memory interface. | Read |
cfg_bank_group_addr_width | 15 | 14 | The number of bank group address bits for the memory devices in your memory interface. | Read |
cfg_cs_addr_width | 18 | 16 | The number of chip select address bits for the memory devices in your memory interface. | Read |
4.4.11. sideband0
address=43(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mr_cmd_trigger | 0 | 0 | Mode Register Command Request. When asserted, indicates user request to execute mode register command. Controller clears bit to 0 when operation is completed. Register offset 37h and 38h must be properly configured before requesting Mode Register Command. Read offset 31h for Mode Register Command Status. | Read/Write |
4.4.12. sideband1
address=44(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_refresh_req | 3 | 0 |
Rank Refresh Request. When asserted, indicates a refresh request to the specific rank. Controller clears this bit to 0 when the refresh is executed. |
Read/Write |
4.4.13. sideband4
address=47(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_self_rfsh_req | 3 | 0 |
Self-refresh request. When asserted, indicates a self-refresh request to DRAM. All 4 bits must be asserted or de-asserted at the same time. User clear to exit self refresh. |
Read/Write |
4.4.14. sideband6
address=49(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mr_cmd_ack | 0 | 0 |
Register Command In Progress. When asserted, indicates Mode Register Command in progress. |
Read |
4.4.15. sideband7
address=50(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_refresh_ack | 0 | 0 |
Refresh In Progress. Acknowledgement signal for refresh request. Indicates that refresh is in progress. Asserts when refresh request is sent out to PHY until tRFC/t_param_arf_to_valid is fulfilled. |
Read |
4.4.16. sideband9
address=52(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_self_rfsh_ack | 0 | 0 |
Self-refresh In Progress. Acknowledgement signal for the self-refresh request. A value of 1 indicates that memory is in self refresh mode. |
Read |
4.4.17. sideband11
address=54(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_auto_pd_ack | 0 | 0 | Auto Power Down In Progress. Acknowledgement signal for auto power down. A value of 1 indicates that the memory is in auto power down mode. | Read |
4.4.18. sideband12
address=55(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mr_cmd_type | 2 | 0 | Register command type. Indicates the type of register command. | Read/Write |
000 - Mode Register Set (DDR3 and DDR4) | ||||
Others - Reserved | ||||
mr_cmd_rank | 6 | 3 | Register command rank. Indicates the rank targeted by the register command. | Read/Write |
0001 - Chip select 0 | ||||
0010 - Chip select 1 | ||||
0011 - Chip select 0 and chip select 1 | ||||
1111 - all chip selects | ||||
Mode Register Set - Any combination of chip selects. |
4.4.19. sideband13
address=56(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mr_cmd_opcode | 31 | 0 | Register Command Opcode. Information used for register command. | Read/Write |
DDR4 | ||||
[26:24] C2:C0 | ||||
[23] ACT | ||||
[22:21] BG1:BG0 | ||||
[20] Reserved | ||||
[19:18] BA1:BA0 | ||||
[17] A17 | ||||
[16] RAS# | ||||
[15] CAS# | ||||
[14] WE# | ||||
[13:0] A13:A0 | ||||
MRS: [22:21] is BG1:BG0, [19:18] is BA1:BA0, [13:0] is Opcode[13:0] | ||||
DDR3 | ||||
[26:21] Reserved | ||||
[20:18] BA2:BA0 | ||||
[17] A14 | ||||
[16] RAS# | ||||
[15] CAS# | ||||
[14] WE# | ||||
[13:0] A13:A0 | ||||
MRS: [19:18] is BA1:BA0, [13:0] is Opcode[13:0] |
4.4.20. sideband14
address=57(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_refresh_cid | 3 | 1 | DDR4 3DS Chip ID Refresh. When asserted, indicates the logical rank chip ID for 3DS refresh. (This field is not applicable for DDR3.) | Read |
4.4.21. dramsts
address=59(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
phy_cal_success | 0 | 0 | This bit is set to 1 if the PHY calibrates successfully. | Read |
phy_cal_fail | 1 | 1 | This bit is set to 1 if the PHY does not calibrate successfully. | Read |
4.4.22. niosreserve0
address=68(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
nios_reserve0 | 15 | 0 | Indicates interface width. | Read |
4.4.23. niosreserve1
address=69(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
nios_reserve1 | 15 | 0 | Indicates ACDS version. | Read |
4.4.24. sideband16
address=79(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
mmr_3ds_refresh_ack | 31 | 0 | DDR4 3DS Refresh Acknowledge. When asserted, indicates acknowledgement for the DDR4 3DS refresh. | Read |
[7:0] Refresh acknowledgement for logical rank [7:0] for physical rank 0. | ||||
[15:8] Refresh acknowledgement for logical rank [7:0] for physical rank 1. | ||||
[23:16] Refresh acknowledgement for logical rank [7:0] for physical rank 2. | ||||
[31:24] Refresh acknowledgement for logical rank [7:0] for physical rank 3. |
4.4.25. ecc3: ECC Error and Interrupt Configuration
address=130(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
cfg_gen_sbe | 0 | 0 | A value of 1 enables the generate SBE feature. Generates a single bit error during the write process. | Read/Write |
cfg_gen_dbe | 1 | 1 | A value of 1 enables the generate DBE feature. Generates a double bit error during the write process. | Read/Write |
cfg_enable_intr | 2 | 2 | A value of 1 enables the interrupt feature. The interrupt signal notifies if an error condition occurs. The condition is configurable. | Read/Write |
cfg_mask_sbe_intr | 3 | 3 | A value of 1 masks the interrupt signal when SBE occurs. | Read/Write |
cfg_mask_dbe_intr | 4 | 4 | A value of 1 masks the interrupt signal when DBE occurs. | Read/Write |
cfg_mask_corr_dropped_intr | 5 | 5 | A value of 1 masks the interrupt signal when the auto correction command can’t be scheduled, due to back-pressure (FIFO full). | Read/Write |
cfg_mask_hmi_intr | 6 | 6 | A value of 1 masks the interrupt signal when the hard memory interface asserts an interrupt signal via the hmi_interrupt port. | Read/Write |
cfg_clr_intr | 7 | 7 | Writing a vale of 1 to this self-clearing bit clears the interrupt signal, error status, and address. | Read/Write |
Reserved | 31 | 8 | Read |
4.4.26. ecc4: Status and Error Information
address=144(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
sts_ecc_intr | 0 | 0 | Indicates the interrupt status; a value of 1 indicates an interrupt occurred. | Read |
sts_sbe_error | 1 | 1 | Indicates the SBE status; a value of 1 indicates SBE occurred. | Read |
sts_dbe_error | 2 | 2 | Indicates the DBE status; a value of 1 indicates DBE occurred. | Read |
sts_corr_dropped | 3 | 3 | Indicates the status of correction command dropped; a value of 1 indicates correction command dropped. | Read |
sts_sbe_count | 7 | 4 | Indicates the number of times SBE error has occurred. The counter will overflow. | Read |
sts_dbe_count | 11 | 8 | Indicates the number of times DBE error has occurred. The counter will overflow. | Read |
sts_corr_dropped_count | 15 | 12 | Indicates the number of times correction command has dropped. The counter will overflow. | Read |
Reserved | 31 | 16 | Read |
4.4.27. ecc5: Address of Most Recent SBE/DBE
address=145(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
sts_err_addr* | 31 | 0 | Address of the most recent single-bit error or double-bit error. | Read |
4.4.28. ecc6: Address of Most Recent Correction Command Dropped
address=146(32 bit)
Field | Bit High | Bit Low | Description | Access |
---|---|---|---|---|
sts_corr_dropped_addr | 31 | 0 | Address of the most recent correction command dropped. | Read |
About ECC Errors in DDR3 and DDR4 Interfaces
ECC errors are categorized as either single-bit errors (which are correctable by ECC code), or double-bit errors (which are not correctable). You can determine whether an ECC error has occurred, by checking the values of the ecc4 register fields sts_ecc_intr, sts_sbe_error, and sts_dbe_error.
- If a double-bit error has occurred, it indicates that the memory is corrupted and cannot be corrected by ECC code. You can choose to reboot your system.
- If a single-bit error has occurred, the controller attempts to
correct the error by performing a write-back to memory using the fixed data plus
an ECC code. The write-back is enabled when you have selected Enable Auto Error Correction to External Memory
on the Controller tab in the IP parameter. The
write-back requires space in the command queue and in the data FIFO buffer;
because
Intel®
Stratix® 10 FPGAs have only 8 command
queues, it is possible that the controller may not be able to schedule the
write-back, in which case the write-back may be dropped. You can determine
whether a write-back has been dropped, by reading the status of the ecc4
register fields ctrl_ecc_sts_corr_dropped_count,
ctrl_ecc_sts_corr_dropped_addr, ctrl_ecc_sts_corr_dropped, and ctrl_ecc_sts_intr registers.
If you discover that a write-back has been dropped, you can do either of two things:
- You can ignore the dropped write-back, because it is a single-bit error that the controller may be able to detect and correct on the next memory read without any intervention – provided the condition does not further deteriorate into a double-bit error.
- You can read the address from the ecc6 register field ctrl_ecc_sts_corr_dropped_addr, and perform a memory write with byte_enable=0, thereby causing the controller to access the memory location again and schedule a new write-back.