AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents Example 2: FPGA Writing Data into HPS SDRAM Directly

In this example the HPS MPU requires access to data that originates from within the FPGA. For the MPU to be able to access the data coherently after it is written, software may need to flush or invalidate cache lines before the transfer starts, to ensure that the SDRAM contains the latest data after it is written. Failing to perform cache operations can cause one or more cache lines to eventually become evicted overwriting the data that was written by the FPGA master.

Figure 14. FPGA Writing Data to HPS FPGA-to-SDRAM PortsThis figure depicts an example of using two of the three F2S ports configured for 128 bits in width.
Note: Like in Example 1: FPGA Reading Data from HPS SDRAM Directly, where the FPGA reads data from the FPGA-to-SDRAM ports, you can maximize write throughput into the HPS SDRAM by using multiple 128-bit FPGA-to-SDRAM ports with at least one master in the FPGA connected to each port.

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