AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
Public
Document Table of Contents

4.1.1. Timing Closure for FPGA Accelerators

The HPS bridges and FPGA-to-SDRAM ports exposed to the FPGA are synchronous and clock crossing is performed within the interface itself. As a result, you must only ensure that both the FPGA-facing logic and your user design close timing in Timing Analyzer. Interrupts are considered asynchronous by the HPS, and as a result the HPS logic resynchronizes them to the internal HPS clock domain so there is no need to close timing for them.

Conduits carry signals that do not fit into any standard interface supported by Platform Designer. Examples of these conduits are HPS peripheral external interfaces routed into the FPGA fabric or the HPS DMA peripheral request interfaces.

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