AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

3.1.4. FPGA-to-SDRAM Ports

GUIDELINE: Use the FPGA-to-SDRAM ports for non-cacheable access to the HPS SDRAM from masters in the FPGA.

The FPGA-to-SDRAM ports allow masters implemented in the FPGA fabric to directly access HPS SDRAM without the transactions flowing through the CCU. There are three FPGA-to-SDRAM ports—FPGA-to-SDRAM0, FPGA-to-SDRAM1, FPGA-to-SDRAM2—supporting 32-, 64-, or 128-bit data paths. These interfaces connect only to the HPS SDRAM subsystem so Intel® recommends to use them in your design if the FPGA needs high-throughput, low-latency access to the HPS SDRAM. The exception to this recommendation is if the FPGA requires cache coherent access to use the FPGA-to-HPS bridge with support for cache coherent accesses using the ACE-Lite protocol.

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