4.1. Timing Considerations
- HPS EMAC PHY Interfaces
- Reduced Media Independent Interface (RMII)
- Reduced Gigabit Media Independent Interface (RGMII)
- PHY Interfaces connected through FPGA I/O
- RMII—Using the MII-to-RMII Adapter
Serial Gigabit Media Independent Interface (SGMII)—Using the GMII-to-SGMII Adapter
- Intel® Management Data Input/Output (MDIO)
For more information about the timing considerations for each of these PHY interfaces, refer to their corresponding sections under the "Design Guidelines for HPS Interfaces" section.
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