AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

4.2. Maximizing Performance

The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial tool to maximize the performance of your design.

For more information about recommended topologies to optimize your system performance, refer to the guidelines in the "Interfacing to the FPGA" section.

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