AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

Download
ID 683117
Date 12/14/2020
Public
Document Table of Contents

3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly

In this example the FPGA requires access to data that is stored in the HPS SDRAM. For the FPGA to access the same copy of the data as the MPU has access to, the L1 data cache and L2 cache need to be flushed if they already have a copy of the data. Once the HPS SDRAM contains the most up-to-date copy of the data, the optimal path for the FPGA to access this data is for FPGA masters to read the data through a FPGA-to-SDRAM port.

Figure 13. FPGA Reading Data from HPS FPGA-to-SDRAM PortsThis figure depicts an example of using two of the three F2S ports configured for 128 bits in width.

Since the Stratix 10 HPS supports up to three 128-bit ports into the SDRAM you can maximize the read throughput by implementing as many as three masters in the FPGA accessing data in the SDRAM through each port. If you decide to implement multiple paths into the SDRAM through the FPGA-to-SDRAM ports ensure that you handle synchronization at a system level since each port is serviced independently from the other. If one port should have a higher priority than the others, then you can adjust the QoS settings for each port shaping the traffic patterns as needed by your application. Intel® recommends to use a burst capable master in the FPGA to read from the FPGA-to-SDRAM ports, capable of posting burst lengths of four beats or larger.5

5 Ensure that Avalon® -MM burst transactions into the HPS do not cross the 4 KB address boundary restriction specified by the AXI protocol.

Did you find the information on this page useful?

Characters remaining:

Feedback Message