Serial Flash Mailbox Client Intel FPGA IP User Guide
|Intel® Quartus® Prime Design Suite 21.1|
|IP Version 19.1.0|
For a complete list of supported flash memory devices refer to the Device Configuration - Support Center web page.
The Serial Flash Mailbox Client Intel FPGA IP core supports:
- Direct flash access (write and read) through the Avalon® Memory-Mapped ( Avalon® MM) interface
- Control register access for other operations through the control and status register (CSR) interface
- Up to 4 kilobytes (KB) or 1024 words data transfers for each quad SPI read and write command
- Opcodes for the following quad SPI operations:
- Set chip select
- Read data from flash
- Write data to flash
- Erase sector
- Read device register
- Write device register
- Send device opcode
Refer to the respective flash device datasheet for a complete list of supported operations for a particular device.
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