Visible to Intel only — GUID: pjt1523459361451
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Serial Flash Mailbox Client IP Modules
Device Family Support
Signals
Register Map
Response Codes
Using the Serial Flash Mailbox Client Intel® FPGA IP
Design Example
Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives
Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Prerequisites
Generating the Configuration Bitstream
Programming the Flash Memory with the Configuration Bitstream
Reading the Flash Memory Device Status Register
Reading the Flash Memory Device ID
Reading the Flash Memory Device ID Using the Control Command
Erasing Flash Memory
Reading Flash Memory
Writing Flash Memory
Visible to Intel only — GUID: pjt1523459361451
Ixiasoft
Control and Status register (CSR) Operation
Follow these steps to perform a read or write to a specific address offset using the Serial Flash Mailbox Client Intel FPGA IP CSR.
- Assert the csr_write or csr_read signals while the csr_waitrequest signal is low. If the csr_waitrequest signal is high, the csr_write or csr_read signals must be kept high until the csr_waitrequest signal goes low.
- Depending on the operation, perform the following steps:
- For read operations, set the address value on the csr_address bus.
- For write operations, set the address value on the csr_address bus and the value data on the csr_writedata bus.
- For read operations, you can retrieve the data after the csr_readdatavalid signal is high.