Serial Flash Mailbox Client Intel® FPGA IP User Guide

ID 683509
Date 4/10/2023
Public
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Control and Status register (CSR) Operation

Follow these steps to perform a read or write to a specific address offset using the Serial Flash Mailbox Client Intel FPGA IP CSR.
  1. Assert the csr_write or csr_read signals while the csr_waitrequest signal is low. If the csr_waitrequest signal is high, the csr_write or csr_read signals must be kept high until the csr_waitrequest signal goes low.
  2. Depending on the operation, perform the following steps:
    • For read operations, set the address value on the csr_address bus.
    • For write operations, set the address value on the csr_address bus and the value data on the csr_writedata bus.
  3. For read operations, you can retrieve the data after the csr_readdatavalid signal is high.