Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Read Operation

Complete the following steps to perform a read operation. The maximum read size is 4 KB (1024 words).
  1. Request exclusive access to the flash memory using the OPEN command.
  2. Select the flash device using the CHIP_SELECT command.
  3. Specify the flash device address using the READ_ADDR command.
  4. Specify the number using the READ_WORDS command.
  5. Flush the read data FIFO before performing any read operations by writing 2b’10 to the READ_OP command.
  6. Start the read operation by transferring data from flash to the read data FIFO by writing 2’b01 to the READ_OP command.
  7. Poll the Rddata valid of the ISR register to when the data stored in read data FIFO is ready to read. You can also read the fill level of the internal read data FIFO using the READ_FIFO_LEVEL command. You can also read the Cmd_err field of the ISR register to check the status of the read transaction. The ISR writes a value of one to the Cmd_err field of the ISR register if a read is unsuccessful. You can also check the Rsp_status field of the STATUS register.
  8. Read the data stored in read data FIFO via read data interfaces.
    1. Assert the rd_mem_read signal while the rd_mem_waitrequest signal is low. If the rd_mem_waitrequest signal is high, the rd_mem_read signal must be kept high until the wr_mem_waitrequest signal goes low.
    2. Set the address value at the rd_mem_address bus.
      Note: Refer to the base address assigned to the rd_mem bus for the Serial Flash Mailbox Client Intel FPGA IP in the Intel® Quartus® Prime Platform Designer for the assigned addresses. .
    3. Read the rd_mem_readdata bus if the rd_mem_readdatavalid signal is asserted.
    4. Repeat steps a to c to continuously read the data from the read data FIFO.
    5. De-assert the rd_mem_read signal once you have completed reading the data from the read data FIFO.
    6. Optional: You can read the fill level of the internal read data FIFO using the READ_FIFO_LEVEL command.
  9. Repeat step 3 to 8 to continue performing read operations.
    Note: You can check the STATUS register each time you send a command to ensure that the command completed successfully.
    Figure 5. Read Operation Example Timing Diagram
  10. Release exclusive access to the flash device using the CLOSE command.
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