Serial Flash Mailbox Client Intel® FPGA IP User Guide

ID 683509
Date 9/26/2022
Public

Prerequisites

You can create a very simple Intel® Quartus® Prime Pro Edition Platform Designer design example to exercise the Serial Flash Mailbox Client Intel® FPGA IP. This design example must meet the following hardware and software requirements:

  • You should be running the Intel® Quartus® Prime Pro Edition software version 18.0 or later.
  • Your Platform Designer design example should include the components in the following figure:
    Figure 6. Required Communication and Host Components for the Serial Flash Mailbox Client Intel® FPGA IP Design Example
    • Instantiate the JTAG to Avalon® Master as host.
    • Instantiate the Serial Flash Mailbox Client Intel® FPGA IP.
    • Connect the Serial Flash Mailbox Client Intel® FPGA IP to JTAG to Avalon® Master Bridge.
    • Set base addresses for csr, rd_mem, and wr_mem.
  • You should be using the Intel® Stratix® 10 SoC Development Kit.

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