Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Writing Flash Memory
Here are the steps to write to flash memory:
# Write Offset 4 to request access to the flash memory device.
master_write_32 $m $AsmiOpen 0x1
# Write Offset 3 to select the 1st flash memory device attached to the IP.
master_write_32 $m $AsmiChipSelect 0x0
# Write Offset 6 to perform write enable operation to the device.
master_write_32 $m $AsmiWrEnable 0x1
# Writing the command argument to Offset 20 (Specify 0x2 to flush out data inside write FIFO)
master_write_32 $m $AsmiWriteOp 0x2
# Pre-store the data that you want to write into flash memory in write data FIFO via the base address of wr_mem in the IP (Specify 0x11223344 to write into write data FIFO)
master_write_32 $m $WR_MEM 0x11223344
# Read Offset 22 to determine the fill level of the internal write data FIFO.
master_read_32 $m $AsmiWriteFifoLevel 1
# Writing the address argument to Offset 21 (specify the device address for write operation to 0x03FF0000)
master_write_32 $m $AsmiWriteAddr 0x03FF0000
# Writing the command argument to Offset 20 (Specify 0x1 to perform write operation)
master_write_32 $m $AsmiWriteOp 0x1
# Write Offset 5 to close access to the flash memory device.
master_write_32 $m $AsmiClose 0x1