Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel FPGA IP User Guide
Serial Flash Mailbox Client Intel FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel FPGA IP User Guide

Register Map

Table 3.  Register Map and Definitions
  • Each address offset in the table represents one word of memory address space.
  • All registers have a default value of 0x0 unless otherwise stated.
Offset Name Field Name R/W Width Bit Description
0 STATUS Rsp_status R 11 10:0 The status of executed commands. Refer to Response Codes for the definitions of response codes.
1 ISR Rddata valid R 1 1 When 1, indicates that readdata is available in the read data FIFO. The READ_FIFO_LEVEL specifies how many words are available in the read data FIFO.
Cmd_err R 1 0 When 1, indicates an that the current command failed. Read the Rsp_status field of the STATUS register to determine the error condition. Assert reset to clear this bit.
2 IER Rdat_valid_en R/W 1 1 The enable bit for read data. The default value is 1.
Cmd_err_en R/W 1 0 The enable for command error responses. The default value is 1.
3 CHIP_SELECT Chip_select R/W 4 3:0 Write the value of the flash device you want to select.
4 OPEN Open W 1 0 Request exclusive access to the flash device. Write 1 to request exclusive access. The Rsp_status field of the STATUS register returns OK the SDM accepts request.

Access to the quad SPI flash memory devices via any mailbox client IP is not available by default in designs that include the HPS, unless you disable the QSPI in HPS software configuration.

5 CLOSE Close W 1 0 Write 1 to close exclusive access to the flash device. The Rsp_status field of the STATUS register returns OK if the SDM accepts request.
6 WR_ENABLE Wr_enable W 1 0 Write 1 to assert the write a enable.
7 WR_STATUS Wr_status W 8 7:0 Writes the STATUS register of the flash memory.
8 RD_STATUS Rd_status R 8 7:0 Rd_status contains the information from read STATUS register operation.1
9 SECTOR_ERASE Sector_address W 32 31:0 Erases 64 KB in the flash memory, regardless of the flash memory sector size. The sector_address must be in most significant byte to least significant byte order.

For example, to erase a sector of a Micron 2 gigabit (Gb) flash at address 0x04FF0000 using the opcode method, complete the following steps:

  1. Get exclusive access to the serial flash device.
  2. Enable the WR_ENABLE: 0x00000001
  3. Set NUMB_BYTES to 4: 0x00000004
  4. Write the CONTROL (opcode) for the sector erase: 0xDC000021
  5. Write the flash address to WRITEDATA_0, the lower 4 bytes of write data: 0x0000FF04

For sequential erase commands in Micron* devices , read bit 7 of the flag status register as detailed in the flash data sheet for the device. Use the CONTROL register read opcode to perform this read.

10 RD_DEVICE_ID Device_id R 32 31:0 Stores the device ID.
11 - 12 Reserved
13 CONTROL Opcode R/W 8 31:24 Opcode of the flash device operation.
Reserved[23:7]
Read_data_en R/W 1 6 When 1, indicates the command has read data.
Write_data_en R/W 1 5 When 1, indicates the command has write data.
Reserved[4:1]
Execute W 1 0 Write 1 to initiate the command.
14 NUMB_BYTES Number_bytes R/W 4 3:0 The number of bytes to write or read from the device register (maximum 8 bytes).
15 WRITEDATA_0 Writedata_0 W 32 31:0 The lower 4 bytes of write data.
16 WRITEDATA_1 Writedata_1 W 32 31:0 The upper 4 bytes of write data.
17 READDATA_0 Readdata_0 R 32 31:0 The lower 4 bytes of read data.
18 READDATA_1 Readdata_1 R 32 31:0 The upper 4 bytes of read data.
19 Reserved
20 WRITE_OP Write_op W 2 1:0

Write 2’b01 to perform write operation with address provided in offset 21 and write data in the FIFO.

Write 2’b10 to flush data in write FIFO .
21 WRITE_ADDR Write_addr W 32 31:0 The device address for write operation.
22 WRITE_FIFO_LEVEL Wr_fifo_level R 32 31:0

Returns the fill level of the internal write data FIFO.

23 READ_OP Read_op W 2 1:0

Write 2’b01 to perform read operation with address provided in offset 24.

Write 2’b10 to flush read data FIFO.
24 READ_ADDR Read_addr R/W 32 31:0 The device address for read operation.
25 READ_WORDS Read_words R/W 32 31:0 Number of words to read from device (maximum is 4 KB.)
26 READ_FIFO_LEVEL Read_fifo_level R 32 31:0 Specifies the fill level of the internal read data FIFO.
Related Information
1 For Micron* devices, the flag status register provides the status of stacked devices. You can access the flag status register using the CONTROL command.
Level Two Title

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