Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Signals

Figure 2. Top-Level Signals
Table 2.  Signal Descriptions
Signal Width Direction Description
Avalon® Memory-Mapped Interface Control and Status Register Signals
csr_address 7 Input Avalon® memory-mapped interface address bus. The address bus uses word (32-bit) addressing.
csr_read 1 Input Avalon® memory-mapped interface read control for the CSR.
csr_readdata 32 Output Avalon® memory-mapped interface read data bus from the CSR.
csr_write 1 Input Avalon® memory-mapped interface write control to the CSR.
csr_writedata 32 Input Avalon® memory-mapped interface write data bus to CSR.
csr_waitrequest 1 Output Avalon® memory-mapped interface wait request control from the CSR.
csr_readdata_valid 1 Output Avalon® memory-mapped interface read data valid that indicates the CSR read data is available.
Avalon® Memory-Mapped Interface Write Data Signals
wr_mem_write 1 Input Avalon® memory-mapped interface write control to the FIFO.
wr_mem_address 1 Input Avalon® memory-mapped interface address.
wr_mem_writedata 32 Input Avalon® memory-mapped interface write data bus to the memory.
wr_mem_waitrequest 1 Output Avalon® memory-mapped interface wait request control from the memory.
Avalon® Memory-Mapped Interface Read Data Signals
rd_mem_read 1 Input Avalon® memory-mapped interface read control to the FIFO.
rd_mem_readdata 32 Output Avalon® memory-mapped interface read data bus from the memory.
rd_mem_readdatavalid 1 Output Avalon® memory-mapped interface read data valid that indicates the memory read data is available.
rd_mem_address 1 Input Avalon® memory-mapped interface address.
Clock and Reset
clk 1 Input Input clock to clock the IP. The maximum frequency supported 250 MHz.
reset 1 Input Synchronous reset to reset the Serial Flash Mailbox Client Intel® FPGA IP.
Note: Refer to the Intel® Stratix® 10 Configuration User Guide for more information about reset in Intel® Stratix® 10 devices.
irq 1 Output The irq signal asserts if the command STATUS is not OK. Read the ISR register Rsp_status field to determine the error.
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