Serial Flash Mailbox Client Intel® FPGA IP User Guide

ID 683509
Date 9/26/2022
Public

Signals

Figure 2. Top-Level Signals
Table 2.  Signal Descriptions
Signal Width Direction Description
Avalon® MM Control and Status Register Signals
csr_address 7 Input Avalon® MM address bus. The address bus uses word (32-bit) addressing.
csr_read 1 Input Avalon® MM read control for the CSR.
csr_readdata 32 Output Avalon® MM read data bus from the CSR.
csr_write 1 Input Avalon® MM write control to the CSR.
csr_writedata 32 Input Avalon® MM write data bus to CSR.
csr_waitrequest 1 Output Avalon® MM wait request control from the CSR.
csr_readdata_valid 1 Output Avalon® MM read data valid that indicates the CSR read data is available.
Avalon® MM Write Data Signals
wr_mem_write 1 Input Avalon® MM write control to the FIFO.
wr_mem_address 1 Input Avalon® MM address.
wr_mem_writedata 32 Input Avalon® MM write data bus to the memory.
wr_mem_waitrequest 1 Output Avalon® MM wait request control from the memory.
Avalon® MM Read Data Signals
rd_mem_read 1 Input Avalon® MM read control to the FIFO.
rd_mem_readdata 32 Output Avalon® MM read data bus from the memory.
rd_mem_readdatavalid 1 Output Avalon® MM read data valid that indicates the memory read data is available.
rd_mem_address 1 Input Avalon® MM address.
Clock and Reset
clk 1 Input Input clock to clock the IP. The maximum frequency supported 250 MHz.
reset 1 Input Synchronous reset to reset the Serial Flash Mailbox Client Intel® FPGA IP.
Note: Refer to the Intel® Stratix® 10 Configuration User Guide for more information about reset in Intel® Stratix® 10 devices.
irq 1 Output The irq signal asserts if the command STATUS is not OK. Read the ISR register Rsp_status field to determine the error.

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