Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Generating the Configuration Bitstream

Use the Programming File Generator to generate configuration bitstream.
  1. On the Intel® Quartus® Prime File menu select Programming File Generator.
  2. For Device family specify Intel® Stratix® 10 .
  3. For Configuration mode specify Active Serial x4
  4. On the Output Files tab, select the JTAG Indirect Configuration File (.jic) output file type.
    Figure 7. Output Files Tab
  5. On the Input Files tab, click Add Bitstream and browse to your .sof.
    Figure 8. Input Files Tab
  6. On the Configuration Device tab select Add Device and select your device from the list of flash devices.
  7. Click Generate to generate the configuration bitstream.
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