Serial Flash Mailbox Client Intel® FPGA IP User Guide

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ID 683509
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
Serial Flash Mailbox Client Intel® FPGA IP User Guide
Serial Flash Mailbox Client Intel® FPGA IP User Guide x
Serial Flash Mailbox Client IP Modules Device Family Support Signals Register Map Response Codes Using the Serial Flash Mailbox Client Intel® FPGA IP Design Example Serial Flash Mailbox Client Intel FPGA IP Core User Guide Archives Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide
Using the Serial Flash Mailbox Client Intel® FPGA IP x
Control and Status register (CSR) Operation Write Operation Read Operation
Design Example x
Prerequisites Generating the Configuration Bitstream Programming the Flash Memory with the Configuration Bitstream Reading the Flash Memory Device Status Register Reading the Flash Memory Device ID Reading the Flash Memory Device ID Using the Control Command Erasing Flash Memory Reading Flash Memory Writing Flash Memory
Serial Flash Mailbox Client Intel® FPGA IP User Guide

Write Operation

Complete the following steps to perform a write operation: The maximum write size is 4 KB (1024 words).
  1. Request exclusive access to the flash memory using the OPEN command.
  2. Select the flash device using the CHIP_SELECT command.
  3. Erase the flash device using the SECTOR_ERASE command.
  4. Flush the write data FIFO by writing 2b’10 using the WRITE_OP command.
  5. Pre-store the data you want to write to the flash device in the write data FIFO via write data interface. Write the write data FIFO:
    Note: The interface backpressures when the write data FIFO is full.
    1. Assert the wr_mem_write signal while the wr_mem_waitrequest signal is low. If the wr_mem_waitrequest signal is high, the wr_mem_write signal must remain high until the wr_mem_waitrequest signal goes low.)
    2. Write the address value to the wr_mem_address bus. Write the data value to wr_mem_writedata bus.
      Note: Refer to the base address assigned to wr_mem bus for Serial Flash Mailbox Client Intel FPGA IP in the Intel® Quartus® Prime Platform Designer for list of address values that you can write.
    3. Repeat step a and b to continuously pre-store the data into the write data FIFO. The FIFO has 1024 words. Consequently, the maximum write is 1024 words.
    4. De-assert the wr_mem_write signal after writing all of the data into the write data FIFO.
    5. Optional: You can read the fill level of the internal write data FIFO using the WRITE_FIFO_LEVEL command determine if the write data FIFO is full.
  6. Read the Rsp_status field of the STATUS register to check the status of the write.
  7. Start the write operation by transferring the data from the write data FIFO into the flash device by writing 2’b01 to the WRITE_OP command.
  8. Poll the Cmd_err field of the ISR register to check the status of the write transaction. The ISR writes a value of one to the Cmd_err field of the ISR register if a write is unsuccessful. You can also check the Rsp_status field of the STATUS register.
  9. Repeat step 3 to 8 to continue to perform the subsequent write operation.
  10. Release exclusive access to the flash device using the CLOSE command.
    Figure 3. Write Operation Example Timing Diagram

    You can use the Serial Flash Mailbox Client Intel FPGA IP to write the raw programming data (.rpd) file into the flash device. By default, the .rpd file is little-endian. To read flash data back correctly, you must transmit the data to flash memory in big-endian format. First reverse the bit order for each byte. Then write the data to flash from the least significant bit (LSB) to most significant bit (MSB) order. The following figure illustrates this process.

    Figure 4.  Connections for Little Endian Format When Bit Swap Is Off
    Note:

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