Serial Flash Mailbox Client Intel® FPGA IP User Guide

ID 683509
Date 9/26/2022
Public

Document Revision History for the Serial Flash Mailbox Client Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.09.26 21.1 Added note in Table Device Family Support.
2020.06.04 21.1 Made the following change:
  • Revised OPEN description in the Register Map and Definitions table. Added statement about designs with HPS.
2020.12.21 20.4 Made the following changes:
  • Updated Serial Flash Mailbox Client Intel® FPGA IP Modules. Added note about quad SPI reset.
  • Updated commands names for consistency across the Register Map and Definitions table, Write Operation, and Read Operation sections.
    • Renamed QSPI_OPEN to OPEN.
    • Renamed QSPI_CLOSE to CLOSE.
    • Renamed QSPI_SET_CS to CHIP_SELECT.
    • Renamed QSPI_ERASE to SECTOR_ERASE.
  • Removed reference to an obsolete AN 891 application note. Added reference to the Intel® Stratix® 10 Configuration User Guide that contains the reset information.
  • Corrected maximum size for write/read operation to 1024 words.
2019.12.11 19.3 Corrected definition of the SECTOR_ERASE command. This command performs a 64 KB erase, regardless of the actual sector size for a particular flash vendor.
2019.11.26 19.3 Removed Operations topic. The Serial Flash Mailbox Client Intel FPGA IP User Guide does not support these commands.
2019.09.30 19.3 Made the following changes:
  • Changed the name of this IP from Stratix 10 Serial Flash Mailbox Client Intel FPGA IP to Serial Flash Mailbox Client Intel FPGA IP.
  • Added support for Micron and Macronix flash devices.
  • Added Operation Commands topic covering the quad SPI commands available to access flash memory devices.
  • Added the missingirq signal description.
  • Added Serial Flash Mailbox Client topic.
  • Made the following changes to the Write Operation and Read Operation steps:
    1. The operations include the QSPI_OPEN and QSPI_SET_CS commands before specifying the flash address.
    2. The operations include the QSPI_CLOSE command after completing the write or read.
  • Corrected bit ordering for the SECTOR_ERASE and RD_DEVICE_ID commands. The correct bit ordering is [31:0].
  • Made the sector erase command mandatory for write operations.
  • Removed references to electrically programmable configuration quad-serial low voltage (EPCQ-L) devices. As of 2018, EPCQ-L are obsolete.
  • Added an example to illustrate bit swapping for the .rpd format which is little endian.
  • Edited the entire user guide for clarity and style.
  • Corrected minor errors and typos.
2019.05.17 19.1
  • Updated Table: Signal Description to add a note regarding IP core instantiation guidelines to the reset signal.
  • Added the Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Archives topic.
2019.04.01 19.1 Updated Table: Register Map and Definitions to update the field name for ISR from Cmd_err1 to Cmd_err.
2018.12.24 18.0
  • Added a design example section.
  • Updated Table: Register Map and Definitions.
  • Updated Table: Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Response Codes.
  • Corrected minor typographical errors.
2018.05.07 18.0 Initial release.

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