External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
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6.2.4.4. x4 DIMM Implementation
The necessary remapping is shown in the table below. You can implement this DQS remapping in either RTL logic or in your schematic wiring connections.
DIMM | Intel® Quartus® Prime EMIF IP | |||
---|---|---|---|---|
DQS0_A | DQ[3:0]_A | DQS0 | DQ[3:0]_A | |
DQS5_A | DQ[7:4]_A | DQS1 | DQ[7:4]_A | |
DQS1_A | DQ[11:8]_A | DQS2 | DQ[11:8]_A | |
DQS6_A | DQ[15:12]_A | DQS3 | DQ[15:12]_A | |
DQS2_A | DQ[19:16]_A | DQS4 | DQ[19:16]_A | |
DQS7_A | DQ[23:20]_A | DQS5 | DQ[23:20]_A | |
DQS3_A | DQ[27:24]_A | DQS6 | DQ[27:24]_A | |
DQS8_A | DQ[31:28]_A | DQS7 | DQ[31:28]_A | |
DQS4_A | CB[3:0]_A | DQS8 | CB[3:0]_A | |
DQS9_A | CB[7:4]_A | DQS9 | CB[7:4]_A | |
DQS0_B | DQ[3:0]_B | DQS10 | DQ[3:0]_B | |
DQS5_B | DQ[7:4]_B | DQS11 | DQ[7:4]_B | |
DQS1_B | DQ[11:8]_B | DQS12 | DQ[11:8]_B | |
DQS6_B | DQ[15:12]_B | DQS13 | DQ[15:12]_B | |
DQS2_B | DQ[19:16]_B | DQS14 | DQ[19:16]_B | |
DQS7_B | DQ[23:20]_B | DQS15 | DQ[23:20]_B | |
DQS3_B | DQ[27:24]_B | DQS16 | DQ[27:24]_B | |
DQS8_B | DQ[31:28]_B | DQS17 | DQ[31:28]_B | |
DQS4_B | CB[3:0]_B | DQS18 | CB[3:0]_B | |
DQS9_B | CB[7:4]_B | DQS19 | CB[7:4]_B |
Data Bus Connection Mapping Flow
- Connect all FPGA DQ pins accordingly to DIMM DQ pins. No remapping is required.
- DQS/DQSn remapping is required either on the board schematics or in the RTL code.
When designing a board to support x4 DQS groups, Intel® recommends that you make it compatible for x8 mode, for the following reasons:
- Provides the flexibility of x4 and x8 DIMM support.
- Allows use of x8 DQS group connectivity rules.
- Allows use of x8 timing rules for matching. Adhere to x4/x8 interoperability rules when designing a DIMM interface, even if the primary use case is to support x4 DIMMs only, because doing so facilitates debug and future migration capabilities. Regardless, the rules for length matching for two nibbles in a x4 interface must match those of the signals for a corresponding x8 interface, as the data terminations are turned on and off at the same time for both x4 DQS groups in an I/O lane. If the two x4 DQS groups were to have significantly different trace delays, it could adversely affect signal integrity. Trace delays for two nibbles packed within the IO12 lanes are matched using the same guidelines as a single x8 byte lane.