External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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4.2.10. s0_axil_rst_n for EMIF

Axilite reset interface

Table 27.  Table 39.  Interface: s0_axil_rst_nInterface type: reset
Port Name Direction Description
s0_axil_rst_n input Axilite reset