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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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6.2.4.2. DDR4 Data Width Mapping
Intel Agilex® 7 M-Series devices do not support flexible data lanes placement. Only fixed byte lanes within the I/O bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an I/O bank.
Controller | Address/Command Scheme | Data Width Usage | BL7 [P95:P84] | BL6 [P83:P72] | BL5 [P71:P60] | BL4 [P59:P48] | BL3 [P47:P36] | BL2 [P35:P24] | BL1 [P23:P12] | BL0 [P11:P0] |
---|---|---|---|---|---|---|---|---|---|---|
Primary | Scheme 2 | DDR4 x16 | GPIO 2 | GPIO 2 | GPIO 2 | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
Scheme 1 | GPIO 2 | GPIO 2 | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 1a | GPIO 2 | GPIO 2 | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 3 | GPIO 2 | GPIO 2 | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 3a | GPIO 2 | GPIO 2 | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 2 | DDR4 x16 + ECC | GPIO 2 | GPIO 2 | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Scheme 1 | GPIO 2 | DQ[ECC] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 1a | GPIO 2 | DQ[ECC] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 3 | GPIO 2 | DQ[ECC] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 3a | GPIO 2 | DQ[ECC] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 2 | DDR4 x32 | GPIO 2 | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Scheme 1 | DQ[3] | DQ[2] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 1a | DQ[3] | DQ[2] | DQ[1] | DQ[0] | AC2 | AC1 | AC0 | AC3 | ||
Scheme 2 | DDR4 x32 + ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Primary + Secondary | Scheme 2 | DDR4 x40 1 | sDQ[0] | wDQ[3] | wDQ[2] | wDQ[1] | AC2 | AC1 | AC0 | wDQ[0] |
Note:
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