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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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11.2.2. Vendor Memory Model
Contact the memory vendor directly, because many additional models are available from the vendor's support system.
When using memory vendor models, ensure that the model is correctly defined for the following characteristics:
- Speed grade
- Organization
- Memory allocation
- Maximum memory usage
- Number of ranks on a DIMM
- Buffering on the DIMM
- ECC
Note: Refer to the readme.txt file supplied with the memory vendor model, for more information about how to define this information for your configuration. Also refer to Transcript Window messages, for more information.
Note: Intel® does not provide support for vendor-specific memory models.
During simulation vendor models output a wealth of information regarding any device violations that may occur because of incorrectly parameterized IP.