External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins

Any I/O banks that do not support transceiver operations in Intel Agilex® 7 M-Series FPGAs support external memory interfaces.

However, RDQS (read data strobe), WCK (write clock),and DQ (data) pins are listed in the device pin tables and are fixed at specific locations in the device. You must adhere to these pin locations to optimize routing, minimize skew, and maximize margins. Always check the pin table for the actual locations of the DQS and DQ pins.

Note: Maximum interface width varies from device to device depending on the number of I/O pins and DQS or DQ groups available. Achievable interface width also depends on the number of address and command pins that the design requires. To ensure adequate PLL, clock, and device routing resources are available, you should always test fit any IP in the Intel® Quartus® Prime software before PCB sign-off.