External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents

6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.

Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.