External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents

3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem

In Intel Agilex® 7 M-Series devices, the I/O subsystem consists of two rows at the edge of the core.

The I/O subsystem provides the following features:

  • General-purpose I/O registers and I/O buffers
  • Compensation Block (Comp block)
    • On-chip termination control (OCT)
  • I/O PLLs
    • I/O Bank I/O PLL for external memory interfaces and user logic
    • Fabric-feeding for non-EMIF/non-LVDS SERDES IP applications
  • True differential signaling
  • External memory interface components, as follows:
    • A Primary hard memory controller, which has connectivity to 8 lanes (up to 4 byte lanes for data, and optionally one additional lane for out-of-band ECC data)
    • A Secondary hard memory controller, which has connectivity to 4 lanes (up to 2 byte lanes for data)
    • Hard PHY
    • Hard Nios® processor and calibration logic
    • DLL