External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents General Guidelines - DDR4

Observe the following general guidelines when placing pins for your Intel Agilex® 7 M-Series external memory interface.
  • EMIF IP pin-out requirements for the Intel Agilex® 7 M-Series Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Intel® Quartus® Prime Pro Edition IP file (.qip), based on the IP configuration.
  • PHY only, RLDRAMx, and QDRx are not supported with HPS.
  1. Ensure that the pins of a single external memory interface reside on the same edge I/O.
  2. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the table in the Address and Command Pin Placement for DDR4 topic.
  3. Not every byte lane can function as an address and command lane or a data lane. The pin assignment must adhere to the DDR4 data width mapping defined in DDR4 Data Width Mapping .
  4. A byte lane must not be used by both address and command pins and data pins.
  5. An I/O 96 bank cannot be used for more than one interface – meaning that two sub-banks belonging to two different EMIF interfaces are not permitted.
  6. Sharing of byte lanes within a sub-bank for two different interfaces is not permitted; you can assign byte lanes within a sub-bank to one EMIF interface only.
  7. Any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin.
    • When the network-on-a-chip (NoC) is used, the use of initiator may block the byte lane in the I/O bank adjacent to the sector where the initiator is located:
      • initiator 0 blocks the access for byte lane (or I/O lane) BL4, BL5, BL6, and partial BL7 (pin index 48 to 88 in the IO96 bank).
      • initiator 1 blocks the access to the fabric AXI command/control port for the primary/secondary controller in the same I/O bank, making the hard controller unavailable for EMIF purposes.
      • initiator 2 blocks the access for BL0,1,2,3 (P0 to P47).
  8. All address and command pins and their associated clock pins (CK and CK#) must reside within a single sub-bank. Refer to the table in DDR4 Data Width Mapping for the supported address and command and data lane placements for DDR4.
  9. An external memory interface can occupy one or more banks on the same edge. When an interface must occupy multiple banks, ensure the following:
    • That the banks are adjacent to one another.
    • That you used only the supported data width mapping as defined in the table in DDR4 Data Width Mapping . Be aware that not every byte lane can be used as an address and command lane or a data lane.
    The following figure shows one possible pin placement for a DDR4 x72 interface on Bank 2C and Bank 2D.
    Figure 12. x72 DDR4 Pin Placement using Bank 2C and 2D
  10. Place read data groups according to the DQS grouping in the pin table and the Pin Planner. Read data strobes (such as DQS and DQS#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
    Note: For DDR4 interfaces with x4 components, you can use the strobe pins with either of the upper or lower DQ nibbles that are placed within a x8 DQS group in an I/O lane. You must place the DQ pins and associated strobes entirely in either the upper or lower half of a 12-bit bank sub-group.
    Consult the pin table for your device to identify the association between DQ pins and DQS pins for x4 mode operation. Additional restrictions apply for x4/x8 DIMM interoperability.
  11. One of the sub-banks in the device (typically the left sub-bank within corner Bank 3A) may not be available if you use certain device configuration schemes. For some schemes, there may be one byte lane available for EMIF data group:
    • AVST-8 – This is contained entirely within the SDM, therefore all lanes of sub-bank 3A can be used by the external memory interface.
    • AVST-32 – Byte lanes 4, 5, 6, and 7 are all effectively occupied and are not usable by the external memory interface.
    • AVST-16 – Byte lanes 6 contains SDM_DATA[25:16], and is not used by AVSTx16. However, the external memory interface cannot use byte lane 6 when byte lanes 4 and 5 are not usable for EMIF purposes.