External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents DDR5 Interface x8 Data Lane

A byte lane in an external memory interface consists of 12 signal pins, denoted 0-11.

For DDR5 interfaces composed of ×8 devices, two pins are reserved for DQS-T and DQS-C signals, one pin is reserved for the optional DM signal, one pin must be reserved, and the remaining eight pins are for DQ signals. One-byte data lane must be assigned for each byte lane, where the byte lane covers DQ [0:7], DQS_T/DQS_C and DM_N. The following are EMIF I/O pin swapping restrictions applicable to a DDR5 interface with a ×8 data lane:

  • DQS_T must go to pin 4 in IO12 pins.
  • DQS_C must go to pin 5 in IO12 pins.
  • DM_N must go to pin 6 in IO12 pins. If the interface does not use the DM_N pin, this pin 6 in IO12 lane must remain unconnected.
  • Pin 7 in IO12 lane remains unconnected. Intel® recommends that you connect this pin 7 to the TDQS dummy load of the memory component and route it as a differential trace along with DM_N (pin 6). This facilitates ×4 or ×8 data interoperability in DIMMs configuration.
  • You can connect data byte (DQ [0:7]) to any pins [0,1,2,3,8,9,10,11] in the byte lane. Any permutation within selected pins is permitted.
Table 108.  Pin Swapping Rules for DDR5 x8 Interfaces
Pin Index Within Byte Lane DDR5 x8 Data Lane Function Swap Consideration
0 DQ Pin Swap group A
1 DQ Pin Swap group A
2 DQ Pin Swap group A
3 DQ Pin Swap group A
4 DQS_T Pin Fixed location (not swappable)
5 DQS_C Pin Fixed location (not swappable)
6 DM Pin Fixed location (not swappable)
7 Unused Fixed location (not swappable)
8 DQ Pin Swap group A
9 DQ Pin Swap group A
10 DQ Pin Swap group A
11 DQ Pin Swap group A