External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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4.1.11. s0_axil for EMIF

Fabric (i.e. NOC-bypass) axilite interface to the IOSSM, including the EMIF mailbox and the calbus bridge

Table 28.  Table 40.  Interface: s0_axilInterface type: axi4lite
Port Name Direction Description
s0_axil_awaddr input Write Address
s0_axil_awvalid input Write Address Valid
s0_axil_awready output Write Address Ready
s0_axil_wdata input Write Data
s0_axil_wstrb input Write Strobes
s0_axil_wvalid input Write Valid
s0_axil_wready output Write Ready
s0_axil_bresp output Write Response
s0_axil_bvalid output Write Response Valid
s0_axil_bready input Response Ready
s0_axil_araddr input Read Address
s0_axil_arvalid input Read Address Valid
s0_axil_arready output Read Address Ready
s0_axil_rdata output Read Data
s0_axil_rresp output Read Response
s0_axil_rvalid output Read Valid
s0_axil_rready input Read Ready
s0_axil_awprot input Write Protection Type
s0_axil_arprot input Read Protection Type