External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents DDR5 Address and Command and CLK Lane

Address and command and control signals in a bank cannot be swapped.

Pin mapping must adhere to the requirements defined in the table in the Address and Command Pin Placement for DDR5 topic.

You cannot swap address and command lanes. You cannot swap among AC0/AC1 lanes. The address and command lane placement must adhere to the specific placement defined in the table in the DDR5 Data Width Mapping topic.

The T and C lanes for the CK_T/_C cannot be swapped with each other, nor can the T and C lanes for the DQS_T/DQS_C be swapped with each other.