Visible to Intel only — GUID: mcd1678203113221
Ixiasoft
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
Visible to Intel only — GUID: mcd1678203113221
Ixiasoft
3.1.3.2. DDR5 Pin Placement
Lane Number | Pin Index | x32+ECC * | x 32 | 2ch x16 | x16 + ECC * | x16 |
---|---|---|---|---|---|---|
BL7 | 95 | MEM_1_MEM_DQ[15] | ||||
94 | MEM_1_MEM_DQ[14] | |||||
93 | MEM_1_MEM_DQ[13] | |||||
92 | MEM_1_MEM_DQ[12] | |||||
91 | ||||||
90 | MEM_1_MEM_DM_N[1] | |||||
89 | MEM_1_MEM_DQS_C[1] | |||||
88 | MEM_1_MEM_DQS_T[1] | |||||
87 | MEM_1_MEM_DQ[11] | |||||
86 | MEM_1_MEM_DQ[10] | |||||
85 | MEM_1_MEM_DQ[9] | |||||
84 | MEM_1_MEM_DQ[8] | |||||
BL6 | 83 | MEM_DQ[39]* | MEM_1_MEM_DQ[7] | |||
82 | MEM_DQ[38]* | MEM_1_MEM_DQ[6] | ||||
81 | MEM_DQ[37]* | MEM_1_MEM_DQ[5] | ||||
80 | MEM_DQ[36]* | MEM_1_MEM_DQ[4] | ||||
79 | ||||||
78 | MEM_DM_N[4] | MEM_1_MEM_DM_N[0] | ||||
77 | MEM_DQS_C[4] | MEM_1_MEM_DQS_C[0] | ||||
76 | MEM_DQS_T[4] | MEM_1_MEM_DQS_T[0] | ||||
75 | MEM_DQ[35]* | MEM_1_MEM_DQ[3] | ||||
74 | MEM_DQ[34]* | MEM_1_MEM_DQ[2] | ||||
73 | MEM_DQ[33]* | MEM_1_MEM_DQ[1] | ||||
72 | MEM_DQ[32]* | MEM_1_MEM_DQ[0] | ||||
BL5 | 71 | MEM_DQ[31] | MEM_DQ[31] | MEM_1_CK_C[1] | ||
70 | MEM_DQ[30] | MEM_DQ[30] | MEM_1_CK_T[1] | |||
69 | MEM_DQ[29] | MEM_DQ[29] | MEM_1_MEM_CS_N[0] | |||
68 | MEM_DQ[28] | MEM_DQ[28] | MEM_1_MEM_CS_N[1] | |||
67 | MEM_1_CK_C[0] | |||||
66 | MEM_DM_N[3] | MEM_DM_N[3] | MEM_1_CK_T[0] | |||
65 | MEM_DQS_C[3] | MEM_DQS_C[3] | MEM_1_MEM_CA[12] | |||
64 | MEM_DQS_T[3] | MEM_DQS_T[3] | MEM_1_MEM_CA[11] | |||
63 | MEM_DQ[27] | MEM_DQ[27] | MEM_1_RESET_N | |||
62 | MEM_DQ[26] | MEM_DQ[26] | OCT_1_OCT_RZQIN | |||
61 | MEM_DQ[25] | MEM_DQ[25] | MEM_1_ALERT_N | |||
60 | MEM_DQ[24] | MEM_DQ[24] | MEM_1_MEM_CA[10] | |||
BL4 | 59 | MEM_DQ[23] | MEM_DQ[23] | Differential "NSide" Reference Clock Input Site |
MEM_DQ[23]* | |
58 | MEM_DQ[22] | MEM_DQ[22] | Differential "PSide" Reference Clock Input Site |
MEM_DQ[22]* | ||
57 | MEM_DQ[21] | MEM_DQ[21] | MEM_1_MEM_CA[9] | MEM_DQ[21]* | ||
56 | MEM_DQ[20] | MEM_DQ[20] | MEM_1_MEM_CA[8] | MEM_DQ[20]* | ||
55 | MEM_1_MEM_CA[7] | |||||
54 | MEM_DM_N[2] | MEM_DM_N[2] | MEM_1_MEM_CA[6] | MEM_DM_N[2] | ||
53 | MEM_DQS_C[2] | MEM_DQS_C[2] | MEM_1_MEM_CA[5] | MEM_DQS_C[2] | ||
52 | MEM_DQS_T[2] | MEM_DQS_T[2] | MEM_1_MEM_CA[4] | MEM_DQS_T[2] | ||
51 | MEM_DQ[19] | MEM_DQ[19] | MEM_1_MEM_CA[3] | MEM_DQ[19]* | ||
50 | MEM_DQ[18] | MEM_DQ[18] | MEM_1_MEM_CA[2] | MEM_DQ[18]* | ||
49 | MEM_DQ[17] | MEM_DQ[17] | MEM_1_MEM_CA[1] | MEM_DQ[17]* | ||
48 | MEM_DQ[16] | MEM_DQ[16] | MEM_1_MEM_CA[0] | MEM_DQ[16]* | ||
BL3 | 47 | MEM_CK_C[1] | MEM_CK_C[1] | MEM_0_CK_C[1] | MEM_CK_C[1] | MEM_CK_C[1] |
46 | MEM_CK_T[1] | MEM_CK_T[1] | MEM_0_CK_T[1] | MEM_CK_T[1] | MEM_CK_T[1] | |
45 | MEM_CS_N[0] | MEM_CS_N[0] | MEM_0_MEM_CS_N[0] | MEM_CS_N[0] | MEM_CS_N[0] | |
44 | MEM_CS_N[1] | MEM_CS_N[1] | MEM_0_MEM_CS_N[1] | MEM_CS_N[1] | MEM_CS_N[1] | |
43 | MEM_CK_C[0] | MEM_CK_C[0] | MEM_0_CK_C[0] | MEM_CK_C[0] | MEM_CK_C[0] | |
42 | MEM_CK_T[0] | MEM_CK_T[0] | MEM_0_CK_T[0] | MEM_CK_T[0] | MEM_CK_T[0] | |
41 | MEM_CA[12] | MEM_CA[12] | MEM_0_MEM_CA[12] | MEM_CA[12] | MEM_CA[12] | |
40 | MEM_CA[11] | MEM_CA[11] | MEM_0_MEM_CA[11] | MEM_CA[11] | MEM_CA[11] | |
39 | MEM_RESET_N[0] | MEM_RESET_N[0] | MEM_0_RESET_N | MEM_RESET_N[0] | MEM_RESET_N[0] | |
38 | RZQ Site | RZQ Site | OCT_0_OCT_RZQIN | RZQ Site | RZQ Site | |
37 | MEM_ALERT_N[0] | MEM_ALERT_N[0] | MEM_0_ALERT_N | MEM_ALERT_N[0] | MEM_ALERT_N[0] | |
36 | MEM_CA[10] | MEM_CA[10] | MEM_0_MEM_CA[10] | MEM_CA[10] | MEM_CA[10] | |
BL2 | 35 | Differential "N-Side" Reference Clock Input Site | Differential "N-Side" Reference Clock Input Site | Differential "NSide" Reference Clock Input Site |
Differential "N-Side" Reference Clock Input Site | Differential "N-Side" Reference Clock Input Site |
34 | Differential "P-Side" Reference Clock Input Site | Differential "P-Side" Reference Clock Input Site | Differential "PSide" Reference Clock Input Site |
Differential "P-Side" Reference Clock Input Site | Differential "P-Side" Reference Clock Input Site | |
33 | MEM_CA[9] | MEM_CA[9] | MEM_0_MEM_CA[9] | MEM_CA[9] | MEM_CA[9] | |
32 | MEM_CA[8] | MEM_CA[8] | MEM_0_MEM_CA[8] | MEM_CA[8] | MEM_CA[8] | |
31 | MEM_CA[7] | MEM_CA[7] | MEM_0_MEM_CA[7] | MEM_CA[7] | MEM_CA[7] | |
30 | MEM_CA[6] | MEM_CA[6] | MEM_0_MEM_CA[6] | MEM_CA[6] | MEM_CA[6] | |
29 | MEM_CA[5] | MEM_CA[5] | MEM_0_MEM_CA[5] | MEM_CA[5] | MEM_CA[5] | |
28 | MEM_CA[4] | MEM_CA[4] | MEM_0_MEM_CA[4] | MEM_CA[4] | MEM_CA[4] | |
27 | MEM_CA[3] | MEM_CA[3] | MEM_0_MEM_CA[3] | MEM_CA[3] | MEM_CA[3] | |
26 | MEM_CA[2] | MEM_CA[2] | MEM_0_MEM_CA[2] | MEM_CA[2] | MEM_CA[2] | |
25 | MEM_CA[1] | MEM_CA[1] | MEM_0_MEM_CA[1] | MEM_CA[1] | MEM_CA[1] | |
24 | MEM_CA[0] | MEM_CA[0] | MEM_0_MEM_CA[0] | MEM_CA[0] | MEM_CA[0] | |
BL1 | 23 | MEM_DQ[7] | MEM_DQ[7] | MEM_0_MEM_DQ[7] | MEM_DQ[7] | MEM_DQ[7] |
22 | MEM_DQ[6] | MEM_DQ[6] | MEM_0_MEM_DQ[6] | MEM_DQ[6] | MEM_DQ[6] | |
21 | MEM_DQ[5] | MEM_DQ[5] | MEM_0_MEM_DQ[5] | MEM_DQ[5] | MEM_DQ[5] | |
20 | MEM_DQ[4] | MEM_DQ[4] | MEM_0_MEM_DQ[4] | MEM_DQ[4] | MEM_DQ[4] | |
19 | ||||||
18 | MEM_DM_N[0] | MEM_DM_N[0] | MEM_0_MEM_DM_N[0] | MEM_DM_N[0] | MEM_DM_N[0] | |
17 | MEM_DQS_C[0] | MEM_DQS_C[0] | MEM_0_MEM_DQS_C[0] | MEM_DQS_C[0] | MEM_DQS_C[0] | |
16 | MEM_DQS_T[0] | MEM_DQS_T[0] | MEM_0_MEM_DQS_T[0] | MEM_DQS_T[0] | MEM_DQS_T[0] | |
15 | MEM_DQ[3] | MEM_DQ[3] | MEM_0_MEM_DQ[3] | MEM_DQ[3] | MEM_DQ[3] | |
14 | MEM_DQ[2] | MEM_DQ[2] | MEM_0_MEM_DQ[2] | MEM_DQ[2] | MEM_DQ[2] | |
13 | MEM_DQ[1] | MEM_DQ[1] | MEM_0_MEM_DQ[1] | MEM_DQ[1] | MEM_DQ[1] | |
12 | MEM_DQ[0] | MEM_DQ[0] | MEM_0_MEM_DQ[0] | MEM_DQ[0] | MEM_DQ[0] | |
BL0 | 11 | MEM_DQ[15] | MEM_DQ[15] | MEM_0_MEM_DQ[15] | MEM_DQ[15] | MEM_DQ[15] |
10 | MEM_DQ[14] | MEM_DQ[14] | MEM_0_MEM_DQ[14] | MEM_DQ[14] | MEM_DQ[14] | |
9 | MEM_DQ[13] | MEM_DQ[13] | MEM_0_MEM_DQ[13] | MEM_DQ[13] | MEM_DQ[13] | |
8 | MEM_DQ[12] | MEM_DQ[12] | MEM_0_MEM_DQ[12] | MEM_DQ[12] | MEM_DQ[12] | |
7 | ||||||
6 | MEM_DM_N[1] | MEM_DM_N[1] | MEM_0_MEM_DM_N[1] | MEM_DM_N[1] | MEM_DM_N[1] | |
5 | MEM_DQS_C[1] | MEM_DQS_C[1] | MEM_0_MEM_DQS_C[1] | MEM_DQS_C[1] | MEM_DQS_C[1] | |
4 | MEM_DQS_T[1] | MEM_DQS_T[1] | MEM_0_MEM_DQS_T[1] | MEM_DQS_T[1] | MEM_DQS_T[1] | |
3 | MEM_DQ[11] | MEM_DQ[11] | MEM_0_MEM_DQ[11] | MEM_DQ[11] | MEM_DQ[11] | |
2 | MEM_DQ[10] | MEM_DQ[10] | MEM_0_MEM_DQ[10] | MEM_DQ[10] | MEM_DQ[10] | |
1 | MEM_DQ[9] | MEM_DQ[9] | MEM_0_MEM_DQ[9] | MEM_DQ[9] | MEM_DQ[9] | |
0 | MEM_DQ[8] | MEM_DQ[8] | MEM_0_MEM_DQ[8] | MEM_DQ[8] | MEM_DQ[8] |
Note: The presence of an asterisk (*) in the above table indicates an ECC byte location.
Did you find the information on this page useful?
Feedback Message
Characters remaining: