External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023
Document Table of Contents OCT

You require an OCT calibration block if you are using an Intel Agilex® 7 M-Series FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design. There are two OCT blocks in an I/O bank, one for each sub-bank.

You must observe the following requirements when using OCT blocks:

  • The I/O bank where you place the OCT calibration block must use the same VCCIO_PIO voltage as the memory interface.
  • The OCT calibration block uses a single fixed RZQ . You must ensure that an external termination resistor is connected to the correct pin for a given OCT block.

For specific pin connection requirements, refer to Specific Pin Connection Requirements .

Did you find the information on this page useful?

Characters remaining:

Feedback Message