External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents

4.3.6. s0_axi4 for EMIF

Fabric (i.e. NOC-bypass) interface to controller

Table 47.  Interface: s0_axi4Interface type: axi4
Port Name Direction Description
s0_axi4_araddr input Read Address
s0_axi4_arburst input Read Burst Type
s0_axi4_arid input Read Write Address ID
s0_axi4_arlen input Read Burst Length
s0_axi4_arlock input Read Lock Type
s0_axi4_arqos input Read Quality of Service
s0_axi4_arsize input Read Burst Size
s0_axi4_arvalid input Read Address Valid
s0_axi4_aruser input Read Address User Signal
s0_axi4_arprot input Read Protection Type
s0_axi4_awaddr input Write Address
s0_axi4_awburst input Write Burst Type
s0_axi4_awid input Write Address ID
s0_axi4_awlen input Write Burst Length
s0_axi4_awlock input Write Lock Type
s0_axi4_awqos input Write Quality of Service
s0_axi4_awsize input Write Burst Size
s0_axi4_awvalid input Write Address Valid
s0_axi4_awuser input Write Address User Signal
s0_axi4_awprot input Write Protection Type
s0_axi4_bready input Response Ready
s0_axi4_rready input Read Ready
s0_axi4_wdata input Write Data
s0_axi4_wstrb input Write Strobes
s0_axi4_wlast input Write Last
s0_axi4_wvalid input Write Valid
s0_axi4_wuser input Write User Signal
s0_axi4_ruser output Ready User Signal
s0_axi4_arready output Read Address Ready
s0_axi4_awready output Write Address Ready
s0_axi4_bid output Response ID
s0_axi4_bresp output Write Response
s0_axi4_bvalid output Write Response Valid
s0_axi4_rdata output Read Data
s0_axi4_rid output Read ID
s0_axi4_rlast output Read Last
s0_axi4_rresp output Read Response
s0_axi4_rvalid output Read Valid
s0_axi4_wready output Write Ready