External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP

To simulate your design you require the following components:
  • A simulator—The simulator must be an Intel-supported Verilog HDL simulator:
    • Siemens EDA* ModelSim
    • Siemens EDA* QuestaSim*
    • Synopsys* VCS/VCS-MX
  • A design using Intel’s External Memory Interface (EMIF) IP
  • An example driver or traffic generator (to initiate read and write transactions)
  • A testbench and a suitable memory simulation model

The Intel External Memory Interface IP is not compatible with the Platform Designer Testbench System. Instead, use the simulation design example from your generated IP to validate memory interface operation, or as a reference for creating a full simulatable design. The provided simulation design example contains the generated memory interface, a memory model, and a traffic generator. For more information about the EMIF simulation design example, refer to the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide.

Memory Simulation Models

There are two types of memory simulation models that you can use:

  • Intel-provided generic memory model
  • Vendor-specific memory model

The Intel® Quartus® Prime software generates the generic memory simulation model with the simulation design example. The model adheres to all the memory protocol specifications, and can be parameterized.

Vendor-specific memory models are simulation models for specific memory components from memory vendors such as Micron and Samsung. You can obtain these simulation models from the memory vendor's website.

Note: Intel does not provide support for vendor-specific memory models.