External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents Address and Command Pin Placement for DDR5

Table 101.  Address and Command Pin Placement
Address/Command Lane Index Within Byte Lane

Scheme 1


Scheme 2


AC1 11 CK_C[1]/SCL(i3c) SCL (i3c)
10 CK_T[1]/SCL(i3c) SDA (i3c)
9 CS_N[0] CS_N[0]
8 CS_N[1] CS_N[1]
7 CK_C[0] CK_C[0]
6 CK_T[0] CK_T[0]
5 CA[12]  
4 CA[11]  
2 RZQ Site
0 CA[10]  
AC0 11 Differential "N-Side" reference clock input site
10 Differential "P-Side" reference clock input site
9 CA[9] LBD, RSP_A_n
8 CA[8] LBS, RSP_B_n
7 CA[7] PAR_A
6 CA[6] CA[6]
5 CA[5] CA[5]
4 CA[4] CA[4]
3 CA[3] CA[3]
2 CA[2] CA[2]
1 CA[1] CA[1]
0 CA[0] CA[0]

The Intel Agilex® 7 M-Series FPGA DDR5 IP supports fixed Address and Command pin placement as shown in the above table. The IP supports up to 2 ranks for the following schemes:

  • Scheme 1 supports component, UDIMM, and SODIMM.
  • Scheme 2 supports RDIMM.