External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents

2.3. Intel Agilex® 7 M-Series EMIF IP Design Checklist

Refer to the following checklist as a quick reference for information about steps in the EMIF design flow.

Table 2.  EMIF Design Checklist
Design Step Description Resources
Select an FPGA Not all Intel FPGAs support all memory types and configurations. To help with the FPGA selection process, refer to the resources listed in the right column.
Parameterize the IP Correct IP parameterization is important for good EMIF IP operation. The resources listed in the right column define the memory parameters during IP generation.
Generate initial IP and example design After you have parameterized the EMIF IP, you can generate the IP, along with an optional example design. Refer to the Quick-Start Guide for a walkthrough of this process.
Perform functional simulation Simulation of the EMIF design helps to determine correct operation. The resources listed in the right column explain how to perform simulation and what differences exist between simulation and hardware implementation.
Make pin assignments For guidance on pin placement, refer to the resources listed in the right column.
Perform board simulation Board simulation helps determine optimal settings for signal integrity, drive strength, as well as sufficient timing margins and eye openings. For guidance on board simulation, refer to the resources listed in the right column.
Verify timing closure For information regarding compilation, system-level timing closure and timing reports refer to the Timing Closure section of this User Guide.
Run the design on hardware For instructions on how to program a FPGA refer to the Quick-Start section of the Design Example User Guide.
Debug issues with preceding steps Operational problems can generally be attributed to one of the following: interface configuration, pin/resource planning, signal integrity, or timing. The resources listed in the right column contain information on typical debug procedures and available tools to help diagnose hardware issues.