External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023
Public
Document Table of Contents

3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment

In Intel Agilex® 7 M-Series external memory interfaces, a global clock network clocks registers inside the FPGA core, and the PHY clock network clocks registers inside the FPGA periphery. Clock phase alignment circuitry employs negative feedback to dynamically adjust the phase of the core clock signal to match the phase of the PHY clock signal.

The clock phase alignment feature effectively eliminates the clock skew effect in all transfers between the core and the periphery, facilitating timing closure. All Intel Agilex® 7 M-Series external memory interfaces employ clock phase alignment circuitry.

Figure 8. Clock Phase Alignment Illustration

Clock Phase Alignment Illustration

Figure 9. Effect of Clock Phase Alignment

Clock Phase Alignment Timing Diagrams

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