External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.9. User Clock in Different Core Access Modes

The EMIF IP for Intel Agilex® 7 M-Series devices supports three user access modes.
  • Synchronous fabric clocking, where the EMIF IP provides a user clock.
    • The user clock frequency is limited by the maximum core-to-periphery (C2P) and periphery-to-core (P2) frequency of 400 MHz.
    • In DDR4, the user clock frequency will be one-quarter of the memory clock frequency ((mem_CK)/4).
    • In DDR5 and LPDDR5, the user clock frequency will be one-eighth of the memory clock frequency ((mem CK)/8).
  • Asynchronous fabric clocking, where you provide the clock to the EMIF IP.
    • The asynchronous user clock can come from any user clock source on the device.
    • The user clock frequency has no dependency on the memory clock (mem_CK).
  • NoC Mode.

The following figures illustrate the different clocking styles available for the Intel Agilex® 7 M-Series EMIF IP. The NoC mode shown is the simplest NoC mode.

Figure 10. Access Modes

Benefits of Each Access Mode

  • Synchronous fabric clocking is required for DDR4 DIMM.
  • Asynchronous fabric access mode has the lowest latency.
  • NoC mode can achieve the highest bandwidth and efficiency, and has the lowest initiator blockage.