External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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Document Table of Contents Command and Address Signals

Command and address signals in SDRAM devices are clocked into the memory device using the CK_T or CK_C signal. These pins operate at single data rate (SDR) using only one clock edge. The number of address pins depends on the SDRAM device capacity. The address pins are multiplexed, so two clock cycles are required to send the row, column, and bank address.

Although DDR5 operates in fundamentally the same way as other SDRAM, there are no dedicated pins for RAS_N, CAS_N, and WE_N, as those are shared with higher-order address pins. DDR5 has CS_N, CKE, ODT, and RESET_N pins, similar to DDR4. DDR5 also has some additional pins, including the ACT_N (activate) pin and BG (bank group) pins.