External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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4.1.2. core_init_n for EMIF

An input to indicate that core configuration is complete

Table 19.  Interface: core_init_nInterface type: reset
Port Name Direction Description
core_init_n input Core init signal going into EMIF. Used to generate the reset signal on the core-EMIF interface in fabric modes.