External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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9.1.1. Timing Analysis

Timing analysis of Intel Agilex® 7 M-Series EMIF IP is somewhat simpler than that of some earlier device families, because Intel Agilex® 7 M-Series devices have more hardened blocks and fewer soft logic registers to be analyzed, because most are user logic registers.

Your Intel Agilex® 7 M-Series EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.