External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 6/26/2023

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4.2. Intel Agilex® 7 M-Series FPGA EMIF IP for DDR5 Interfaces

The interfaces in the Intel Agilex 7 EMIF Architecture each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types.

Table 29.  Interfaces for Intel Agilex® 7 M-Series FPGA EMIF IP
Interface Name Interface Type Description
ref_clk clock PLL reference clock input
core_init_n reset An input to indicate that core configuration is complete
usr_async_clk clock User clock interface
usr_clk clock User clock interface
usr_rst_n reset User clock domain reset interface
s0_axi4 axi4 Fabric (i.e. NOC-bypass) interface to controller
mem conduit Interface between FPGA and external memory
oct conduit On-Chip Termination (OCT) interface
s0_axil_clk clock Axilite clock interface
s0_axil_rst_n reset Axilite reset interface
s0_axil axi4lite Fabric (i.e. NOC-bypass) axilite interface to the IOSSM, including the EMIF mailbox and the calbus bridge