Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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13. Reset Manager

The reset manager generates module reset signals based on reset requests from the various sources in the HPS, and software writing to the module-reset control registers.

The HPS contains multiple reset domains. Each reset domain can be reset independently. A reset may be initiated externally, internally or through software.
Table 101.  HPS Reset Domains
Reset Domain Reset Source Description
POR

(Power-on Reset)

Secure Device Manager (SDM)

SDM requests reset manager to assert POR reset.

During a voltage tampering or out-of-range event, the SDM asserts POR. When voltage returns to operating range, the POR is de-asserted.

During POR, the entire HPS and FPGA is reset. When the device is released from POR, SDM begins initialization.

System Cold Reset19
  • SDM (HPS mailbox message)
  • HPS_COLD_nRESET pin20
SDM requests reset manager to assert or de-assert cold reset.
System Warm Reset
  • Software requests a warm reset through the EL3 register
  • Request from Cortex-A53 MPCore.
Reset manager asserts warm reset provided that the Cortex-A53 MPCore is idle. During warm reset, the CoreSight logic is not in reset, therefore the debug/trace can continue immediately after reset manager de-asserts warm reset.
Note: An L2 reset must be performed before requesting a warm reset. Before you request L2 reset via software, you must flush L2 using the l2flushen bit of the hdsken register.
Watchdog Reset Watchdog Timeout Event Reset manager asserts watchdog reset based on the watchdog timer register. As the CoreSight logic is not reset, the debug/trace can continue immediately after reset manager de-asserts watchdog reset.
MPU Cold Reset Software requests a cold reset through the COLDMODRST register Reset manager asserts cold reset to the MPU provided that all four cores are idle.
Note: Before you request MPU cold reset via software, you must idle all four cores using a WFI instruction and flush L2 using the l2flushen bit of the hdsken register.
CPU Cold Reset Reset manager asserts cold reset to the requested core provided that that the core and L2 is idle (execute a WFI instruction).
CPU Warm Reset Software requests a warm reset through the MPUMODRST register Reset manager asserts warm reset to the requested core provided that that core is idle (execute a WFI instruction).
Debug Reset Software requests a debug reset through the DBGMODRST register The DBGMODRST register has two dedicated bits, one each for DAP and debug logic. Reset manager asserts reset for both DAP and debug logic. Software must clear debug reset bit to resume debugging.
Note: While the HPS Power-on Reset and System Cold Reset are managed by the SDM, in all cases, the FPGA configuration is not affected by any HPS reset.
19 You may ignore the HPS_COLD_nRESET signal and HPS mailbox reset command when the HPS is not running or the device is being configured.
20 You can assign HPS_COLD_nRESET to an available SDM I/O pin. This pin serves both as an input to reset the HPS and as an output to the external system to indicate that the HPS is in reset. Do not connect HPS_COLD_nRESET to the external flash. The SDM controls the reset of the external flash separately. You can configure this pin using the Intel® Quartus® Prime Pro Edition, under Device and Pin options > Configuration > Configuration pin option.