Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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3.5. Cortex-A53 MPCore Functional Description

The ARM® Cortex® -A53 MPCore is a 64-bit processor that implements the ARM® v8-A architecture. The Cortex® -A53 MPCore™ processor has four cores with an L1 memory system and a single, shared L2 cache.

Table 29.   ARM® Cortex® -A53 MPCore Processor Configuration This table shows the parameters for the ARM® Cortex® -A53 MPCore Processor.

Feature

Configuration

ARM® v8-A architecture, Cortex® -A53 CPUs

4

Instruction cache size per CPU

32 KB, 2-way set associative with a line size of 64 bytes per line

Data cache size per CPU

32 KB, 4-way set associative with a line size of 64 bytes per line

L2 cache size shared among four CPUs

1 MB, 16-way set associative with a line size of 64 bytes per line

Media Processing Engine with NEON* technology in each CPU

Included with support for floating-point operations

ARM® v8-A cryptographic extensions in each CPU

Included

Embedded Trace Macrocell (ETMv4) in each CPU

Included

Cache protection

Included for L1 and L2 cache. See "Cache Protection" section for more information.