Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.5.2. Initialization

After the power and clock to the controller are stable, the controller active‑low reset is asserted. The reset sequence initializes the registers, FIFO buffer pointers, DMA interface controls, and state machines in the controller.
Figure 56. SD/MMC Controller Initialization Sequence

Power-On Reset Sequence

Software must perform the following steps after the power‑on‑reset:
  1. Before enabling power to the card, confirm that the voltage setting to the voltage regulator is correct.
  2. Enable power to the card by setting the power enable bit (power_enable) in the power enable register (pwren) to 1. Wait for the power ramp‑up time before proceeding to the next step.
  3. Set the interrupt masks by resetting the appropriate bits to 0 in the intmask register.
  4. Set the int_enable bit of the ctrl register to 1.
    Note: Intel recommends that you write 0xFFFFFFFF to the rintsts register to clear any pending interrupts before setting the int_enable bit to 1.
  5. Discover the card stack according to the card type. For discovery, you must restrict the clock frequency to 400 kHz in accordance with SD/MMC/CE‑ATA standards. For more information, refer to Enumerated Card Stack.
  6. Set the clock source assignments. Set the card frequency using the clkdiv and clksrc registers of the controller. For more information, refer to Clock Setup.
  7. The following common registers and fields can be set during initialization process:
    • The response timeout field (response_timeout) of the tmout register. A typical value is 0x40.
    • The data timeout field (data_timeout) of the tmout register, highest of the following:
      • 10 * NAC

        NAC = card device total access time

        = 10 * ((TAAC * FOP) + (100 * NSAC))

        where:

        TAAC = Time‑dependent factor of the data access time

        FOP = The card clock frequency used for the card operation

        NSAC = Worst‑case clock rate‑dependent factor of the data access time

      • Host FIFO buffer latency

        On read: Time elapsed before host starts reading from a full FIFO buffer

        On write: Time elapsed before host starts writing to an empty FIFO buffer

    • Debounce counter register (debnce). A typical debounce value is 25 ms.
    • TX watermark field (tx_wmark) of the FIFO threshold watermark register (fifoth). Typically, the threshold value is set to 512, which is half the FIFO buffer depth.
    • RX watermark field (rx_wmark) of the fifoth register. Typically, the threshold value is set to 511.

These registers do not need to be changed with every SD/MMC/CE‑ATA command. Set them to a typical value according to the SD/MMC/CE‑ATA specifications.

Enumerated Card Stack

The card stack performs the following tasks:
  • Discovers the connected card
  • Sets the relative Card Address Register (RCA) in the connected card
  • Reads the card specific information
  • Stores the card specific information locally

The card connected to the controller can be an MMC, CE‑ATA, SD or SDIO (including IO ONLY, MEM ONLY and COMBO) card.

Identifying the Connected Card Type

To identify the connected card type, the following discovery sequence is needed:
  1. Reset the card width 1 or 4 bit (card_width2) and card width 8 bit (card_width1) fields in the ctype register to 0.
  2. Identify the card type as SD, MMC, SDIO or SDIO-COMBO:
    1. Send an SD/SDIO IO_SEND_OP_COND (CMD5) command with argument 0 to the card.
    2. Read resp0 on the controller. The response to the IO_SEND_OP_COND command gives the voltage that the card supports.
    3. Send the IO_SEND_OP_COND command, with the desired voltage window in the arguments. This command sets the voltage window and makes the card exit the initialization state.
    4. Check bit 27 in resp0:
      • If bit 27 is 0, the SDIO card is IO ONLY. In this case, proceed to step 5.
      • If bit 27 is 1, the card type is SDIO COMBO. Continue with the following steps.
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  5. At this point, the software has determined the card type as SD/SDHC, SDIO or SDIO-COMBO. Now it must enumerate the card stack according to the type that has been discovered.
  6. Set the card clock source frequency to the frequency of identification clock rate, 400 KHz. Use one of the following discovery command sequences:
    • For an SD card or an SDIO memory section, send the following SD/SDIO command sequence:
      • GO_IDLE_STATE
      • SEND_IF_COND
      • SD_SEND_OP_COND (ACMD41)
      • ALL_SEND_CID (CMD2)
      • SEND_RELATIVE_ADDR (CMD3)
    • For an SDIO card, send the following command sequence:
      • IO_SEND_OP_COND
      • If the function count is valid, send the SEND_RELATIVE_ADDR command.
    • For an MMC, send the following command sequence:
      • GO_IDLE_STATE
      • SEND_OP_COND (CMD1)
      • ALL_SEND_CID
      • SEND_RELATIVE_ADDR
  7. Change the card clock frequency after discovery by writing a value to the clkdiv register that divides down the sdmmc_clk clock.

    The following list shows typical clock frequencies for various types of cards:

    • SD memory card, 25 MHz
    • MMC card device, 12.5 MHz
    • Full speed SDIO, 25 MHz
    • Low speed SDIO, 400 kHz

Card Type is Either SDIO COMBO or Still in Initialization

Only continue with this step if the SDIO card type is COMBO or there is no response received from the previous IO_SEND_OP_COND command. Otherwise, skip to Step 5 of the Identifying the Connected Card Type section.

  1. Send the SD/SDIO SEND_IF_COND (CMD8) command with the following arguments:
    • Bit[31:12] = 0x0 (reserved bits)
    • Bit[11:8] = 0x1 (supply voltage value)
    • Bit[7:0] = 0xAA (preferred check pattern by SD memory cards compliant with SDIO Simplified Specification Version 2.00 and later.)

    Refer to SDIO Simplified Specification Version 2.00 as described on the SD Association website.

    • If a response is received to the previous SEND_IF_COND command, the card supports SD High-Capacity, compliant with SD Specifications, Part 1, Physical Layer Simplified Specification Version 2.00.
    • If no response is received, proceed to the next decision statement.
  2. Send the SD_SEND_OP_COND (ACMD41) command with the following arguments:
    • Bit[31] = 0x0 (reserved bits)
    • Bit[30] = 0x1 (high capacity status)
    • Bit[29:25] = 0x0 (reserved bits)
    • Bit[24] = 0x1 (S18R ‑‑supports voltage switching for 1.8V)
    • Bit[23:0] = supported voltage range
    • If the previous SD_SEND_OP_COND command receives a response, then the card type is SDHC. Otherwise, the card is MMC or CE-ATA. In either case, skip the following steps and proceed to Step 5 of the Identifying the Connected Card Type section.
    • If the initial SEND_IF_COND command does not receive a response, then the card does not support High Capacity SD2.0. Now, proceed to step 3.
  3. Next, issue the GO_IDLE_STATE command followed by the SD_SEND_OP_COND command with the following arguments:
    • Bit[31] = 0x0 (reserved bits)
    • Bit[30] = 0x0 (high capacity status)
    • Bit[29:24] = 0x0 (reserved bits)
    • Bit[23:0] = supported voltage range

    If a response is received to the previous SD_SEND_OP_COND command, the card is SD type. Otherwise, the card is MMC or CE-ATA.

    Note:
    You must issue the SEND_IF_COND command prior to the first SD_SEND_OP_COND command, to initialize the High Capacity SD memory card. The card returns busy as a response to the SD_SEND_OP_COND command when any of the following conditions are true:
    • The card executes its internal initialization process.
    • A SEND_IF_COND command is not issued before the SD_SEND_OP_COND command.
    • The ACMD41 command is issued. In the command argument, the Host Capacity Support (HCS) bit is set to 0, for a high capacity SD card.

Determine if Card is a CE-ATA 1.1, CE-ATA 1.0, or MMC Device

Use the following sequence to determine whether the card is a CE-ATA 1.1, CE-ATA 1.0, or MMC device:

Determine whether the card is a CE-ATA v1.1 card device by attempting to select ATA mode.

  1. Send the SD/SDIO SEND_IF_COND command, querying byte 504 (S_CMD_SET) of the EXT_CSD register block in the external card.

    If bit 4 is set to 1, the card device supports ATA mode.

  2. Send the SWITCH_FUNC (CMD6) command, setting the ATA bit (bit 4) of the EXT_CSD register slice 191 (CMD_SET) to 1.

    This command selects ATA mode and activates the ATA command set.

  3. You can verify the currently selected mode by reading it back from byte 191 of the EXT_CSD register.
  4. Skip to Step 5 of the Identifying the Connected Card Type section.

    If the card device does not support ATA mode, it might be an MMC card or a CE-ATA v1.0 card. Proceed to the next section to determine whether the card is a CE-ATA 1.0 card device or an MMC card device.

Determine whether the card is a CE-ATA 1.0 card device or an MMC card device by sending the RW_REG command.

If a response is received and the response data contains the CE-ATA signature, the card is a CE-ATA 1.0 card device. Otherwise, the card is an MMC card device.

Clock Setup

The following registers of the SD/MMC controller allow software to select the desired clock frequency for the card:
  • clksrc
  • clkdiv
  • clkena

The controller loads these registers when it receives an update clocks command.

Changing the Card Clock Frequency

To change the card clock frequency, perform the following steps:
  1. Before disabling the clocks, ensure that the card is not busy with any previous data command. To do so, verify that the data_busy bit of the status register (status) is 0.
  2. Reset the cclk_enable bit of the clkena register to 0, to disable the card clock generation.
  3. Reset the clksrc register to 0.
  4. Set the following bits in the cmd register to 1:
    • update_clk_regs_only—Specifies the update clocks command
    • wait_prvdata_complete—Ensures that clock parameters do not change until any ongoing data transfer is complete
    • start_cmd—Initiates the command
  5. Wait until the start_cmd and update_clk_regs_only bits change to 0. There is no interrupt when the clock modification completes. The controller does not set the command_done bit in the rintsts register upon command completion. The controller might signal a hardware lock error if it already has another command in the queue. In this case, return to Step 4.

    For information about hardware lock errors, refer to the "Interrupt and Error Handling" chapter.

  6. Reset the sdmmc_clk_enable bit to 0 in the enable register of the clock manager peripheral PLL group (perpllgrp).
  7. In the control register (ctrl) of the SDMMC controller group (sdmmcgrp) in the system manager, set the drive clock phase shift select (drvsel) and sample clock phase shift select (smplsel) bits to specify the required phase shift value.
  8. Set the sdmmc_clk_enable bit in the Enable register of the clock manager perpllgrp group to 1.
  9. Set the clkdiv register of the controller to the correct divider value for the required clock frequency.
  10. Set the cclk_enable bit of the clkena register to 1, to enable the card clock generation.

    You can also use the clkena register to enable low‑power mode, which automatically stops the sdmmc_cclk_out clock when the card is idle for more than eight clock cycles.

Timing Tuning

This section is pending further information.