Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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12.3.2. FPGA Interface Enables

The system manager can enable or disable interfaces between the FPGA and HPS.

Note: Ensure that the FPGA is configured before enabling the interfaces and that all interfaces between the FPGA and HPS are inactive before disabling them.

You can program the FPGA interface enable registers (fpgaintf_en_*) to enable/disable the following interfaces between the FPGA and HPS:

  • Boundary scan interface
  • Debug interface
  • Trace interface
  • System Trace Macrocell (STM) interface
  • Cross-trigger interface (CTI)
  • NAND interface
  • SD/MMC interface
  • SPI Master interface
  • EMAC interfaces