Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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Document Table of Contents

13.1. Functional Description

The reset manager performs the following functions:
  • Accepts reset requests from the SDM, and software.
  • Generates reset signals to modules in the HPS and to the FPGA fabric. The following actions generate reset signals:
    • Using software to write the MPUMODRST, PER0MODRST, PER1MODRST, BRGMODRST, COLDMODRST, or DBGMODRST module reset control registers.
    • Asserting the HPS_COLD_nRESET signal triggers the reset controller and s2f_cold_rst signal.
  • Provides reset handshaking signals to support system reset behavior.
Figure 34. Reset Manager Block Diagram
Multiple reset requests can be driven to the reset manager at the same time. Higher priority reset requests can preempt lower priority requests if the lower priority request has not been committed, that is if the reset acknowledgment process is incomplete. If a lower priority request is committed, then a higher priority request is delayed until the lower priority reset completes. There is no priority difference among reset requests within the same domain.
Table 102.  Reset Priority
Ongoing Reset Start of New Reset Action Taken by Reset Manager
Cold reset Cold reset The reset manager extends the reset period for all the module reset outputs until all cold reset requests are removed. If a cold reset request is issued while the reset manager is removing other modules out of the reset state, the reset manager returns those modules back to the reset state.
Warm reset Watchdog reset If warm reset is not committed:
  • Execute watchdog reset.
  • Complete the watchdog reset assertion and de-assertion.
If warm reset is committed, queue the watchdog reset and
  • Execute warm reset.
  • Then, complete the pending watchdog reset.
Warm reset Cold reset If warm reset is not committed:
  • Execute cold reset.
  • Complete the cold reset assertion and de-assertion.
If warm reset is committed, queue the cold reset and
  • Execute warm reset.
  • Then, complete the pending cold reset.
Warm reset Any other reset initiated by software Continue warm reset regardless of whether warm reset is committed or not.
Watchdog reset Cold reset If watchdog reset is not committed:
  • Execute cold reset.
  • Complete the cold reset assertion and de-assertion.
If watchdog reset is committed, queue the cold reset and
  • Execute watchdog reset.
  • Then, complete the pending cold reset.
Watchdog reset Warm reset Continue watchdog reset.
Software initiated CPU warm reset Warm reset First, complete software initiated reset and then execute warm reset.
Software initiated POR reset / L2 reset Warm reset First, complete software initiated reset and then execute warm reset.
Software initiated CPU warm reset Watchdog reset Stop software initiated reset, and execute watchdog reset.
Software initiated POR reset Watchdog reset Stop software initiated reset, and execute watchdog reset.
Software initiated CPU warm reset Cold reset Stop software initiated reset, and execute cold reset.
Software initiated L2 reset Cold reset Stop software initiated reset, and execute cold reset.

The reset manager contains the stat register that indicates which reset source caused a reset. After a cold reset completes, the reset manager clears all bits except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the bit corresponding to the source that de-asserts its request last is set.

After a warm reset is complete, the bit(s) that indicate the source of the warm reset are set to 1. A warm reset does not clear any bits in the stat register, therefore you may want clear them after determining the reset source. Any bit can be manually cleared by writing a 1 to it.