Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

13.4.1. HPS-to-FPGA Reset Sequence

During any reset condition that requires the SDM (for example: POR, system cold reset or mailbox message to SDM), the SDM holds the Reset Manager in reset until all reset requests to the SDM have been removed, or for a minimum of 128 boot clocks at 200 MHz. During this time, the Reset Manager asserts s2f_cold_rst, s2f_rst, and s2f_watchdog_rst signals. Thereafter, the Reset Manager releases signals according to the Table: Reset Priority.

During any reset condition that does not require the SDM (for example: system warm reset or watchdog reset), the Reset Manager asserts s2f_rst or s2f_watchdog_rst signal for a minimum of 128 boot clocks at 200 MHz. Thereafter, the Reset Manager releases signals according to the Table: Reset Priority.
Note: The Reset Manager does not release the MPU at the same time as releasing s2f_cold_rst, s2f_rst, or s2f_watchdog_rst. To release the MPU cores out of reset, the Reset Manager waits until the ocramload.done bit is set.