Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5.17. Clock Sources

Four clock inputs exist for the Cortex® -A53 MPCore™ .
Table 38.   Cortex® -A53 Clock Inputs

System Clock Name

Use

mpu_clk

Main clock for the ARM® Cortex® -A53 MPCore processor. This synchronous clock drives each CPU including the L1 cache, the L2 cache controller and the snoop control unit clock.

mpu_ccu_clk

Synchronous clock for the L2 RAM. The L2 RAM is clocked at ½ of the mpu_clk frequency. The 128-bit Cortex® -A53 MPCore™ ACE bus and the system cache coherency unit (CCU), also operate in the mpu_ccu_clk domain.

mpu_periph_clk

Synchronous clock for the peripherals internal to the ARM® Cortex® -A53 MPCore MPU system complex. The peripherals include the generic interrupt controller and internal timers. They are clocked at ¼ of the mpu_clk frequency.

cs_pdbg_clk

Asynchronous clock for debug and performance monitor counters.